Sony Semiconductor Solutions Corporation

Sony Corporation

Yasunori Tsukuda

Yosuke Ueno

Kenichi Takamiya

Yuki Yagishita

Kazutoshi Tomita

Noam Eshel

Takashi Moue

Takeshi Matsunuma

Brian R Carey

Shohei Shimada

Masahiro Ichihashi

Eiichi Nakamoto

Akito Sekiya

Tetsuya Tashiro

Ryuta Okamoto

Sen Yu

Kazuki Akutagawa

Noboru Sakimura

Yannick Baines

[Object] Provided are a light receiving device and a light receiving circuit that are capable of performing highly accurate ranging with an increased field of view (FOV). [Solving Means] A light receiving device according to the present disclosure includes a light detector array including a plurality of pixels each configured to output a pulse in response to a reaction of a light detector with a photon, a counter circuit configured to count the pulse outputted from at least one of the pixels of the light detector array, and a control circuit configured to select, from the light detector array, one of the pixels to be enabled and one of the pixels to be disabled, on the basis of the number of counts of the pulse from the counter circuit.

Light receiving device and light receiving circuit

Optical detection devices wherein a bias voltage of a photoelectric conversion element is accurately adjustable regardless of a quantity of incident light are disclosed. In one example, an optical detection device includes a first pixel that has a photoelectric conversion element for generating a carrier by photoelectric conversion, a second pixel that has a carrier generation unit for generating a carrier by a cause other than photoelectric conversion, and a control circuit that controls a bias voltage applied to each of the photoelectric conversion element and the carrier generation unit, according to the carrier generated by the second pixel. The photoelectric conversion element includes a first photoelectric conversion region and a first pinning film disposed at a position in contact with the first photoelectric conversion region. The carrier generation unit includes a second photoelectric conversion region, and includes a second pinning film that is partially removed.

Optical detection device and electronic apparatus

The present technology relates to a light receiving device and a distance measurement system that enable light to be surely received by a reference pixel. A light receiving device includes a plurality of pixels each including a light receiving element having a light receiving surface, and a light emission source provided on an opposite side of the light receiving surface with respect to the light receiving element. The plurality of pixels includes a first pixel including a light shielding member provided between the light receiving element and the light emission source, and a second pixel including a light guiding unit that is configured to propagate a photon and is provided between the light receiving element and the light emission source. The present technology can be applied to a distance measurement system or the like that detects a distance to a subject in a depth direction, for example, for example.

Light receiving device and distance measurement system

Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

Voltage conversion circuit, solid-state imaging element, and method of controlling voltage conversion circuit

A level shift circuit includes an input section to which input signal of a first power supply system is input, a supply section that includes a pair of nodes, and a regulator. The supply section is connected to one of a pair of power supply lines serving as a second power supply system of which a voltage level is higher than a voltage level of the first power supply system, the supply section supplying a potential of the one of the pair of power supply lines to one of the pair of nodes according to the input signal. The regulator is connected to another of the pair of power supply lines, the regulator regulating current flowing between the one of the pair of nodes that is supplied with the potential of the one of the pair of power supply lines, and the other of the pair of power supply lines.

Level shift circuit and electronic apparatus

The present disclosure relates to an imaging element, a driving method, and electronic equipment that enable imaging to be performed at higher speed. The imaging element includes a pixel array in which a plurality of pixels are arranged in a matrix shape, an AD converter that performs AD conversion in parallel on pixel signals that have been output from the plurality of pixels for each column of the plurality of pixels arranged in the pixel array, and a reference signal generator that generates a reference signal that the AD converter refers to when the AD converter performs AD conversion on a pixel signal for an identical pixel signal, the reference signal having a waveform that includes a slope having a constant gradient. Then, when the AD converter performs, on the identical pixel signal, multi-sampling for performing sampling during a P-phase period and sampling during a D-phase period at least once or more, the reference signal generator generates a reference signal in which, from among a plurality of slopes during the D-phase period, a sampling period of a second slope has been set to be shorter than a sampling period of a first slope. The present technology is applicable, for example, to a CMOS image sensor including a column-parallel ADC.

Imaging element, driving method, and electronic equipment

The present disclosure relates to an imaging device and an electronic device capable of restricting an occurrence of a sunspot phenomenon in a simple configuration. The imaging device includes a sample/hold part that samples and holds a reset voltage as a reset level voltage of a pixel signal and an AD conversion part that analog digital (AD) converts the pixel signal, in which the AD conversion part selects and outputs one of a first output signal as the AD converted pixel signal and a second output signal at a predetermined level on the basis of a comparison result between the reset voltage held by the sample/hold part and a predetermined reference voltage. The technology according to the present disclosure can be applied to a CMOS image sensor, for example.

Imaging device and electronic device

An imaging device comprising a pixel substrate including pixel element circuitry, a logic substrate including read circuitry configured to receive an output signal voltage from the pixel element circuitry, and electrically-conductive material arranged between the pixel substrate and the logic substrate, wherein the electrically-conductive material is configured to transfer at least one reference voltage from the logic substrate to the pixel substrate, wherein the electrically-conductive material comprises a Cu&#x2014;Cu bonding portion.

Stacked imaging device with Cu-Cu bonding portion

The present disclosure relates to a solid-state imaging device, an image pickup apparatus, and an electronic device capable of stably supplying high-speed control signals and clock signals. In the area AD method in which analog-digital conversion of a pixel signal is performed for each ADC area corresponding to a pixel group including a plurality of pixels, a repeater element is regularly arranged in each area group unit including one or more ADC areas, to re-drive control signals for controlling a plurality of the ADC areas. The present disclosure is applicable to a solid-state imaging device.

Solid-state imaging device, image pickup apparatus, and electronic device

There is provided an electronic circuit including a timing signal generation unit for generating a timing signal; a data signal supply unit for synchronizing with the timing signal generated to supply a data signal; a data signal transmission circuit for transmitting the data signal supplied; a timing signal transmission circuit for transmitting the timing signal generated by a circuit having a substantially same delay time as the data signal transmission circuit; and a data holding unit for synchronizing with the timing signal transmitted to hold and output the data signal transmitted. Also, there are provided a solid state image capturing apparatus and a method of controlling the electronic circuit.

Electronic circuit, solid state image capturing apparatus and method of controlling electronic circuit

The present technique relates to a clock generation circuit including a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal, a filter circuit configured to suppress a high frequency component in the phase difference signal, an output circuit configured to modulate the phase difference signal in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal, and a frequency dividing circuit configured to divide a frequency of the output clock signal, at a predetermined frequency dividing ratio, and feed it back to the phase comparison circuit.

Clock generation circuit

A signal generation circuit includes a phase difference detector configured to detect a phase difference between a certain oscillation signal of a plurality of oscillation signals and a predetermined reference signal; an oscillator to which a plurality of delay elements are connected annularly, the oscillator being configured to generate the plurality of oscillation signals depending on the detected phase difference; a low-speed signal generation circuit configured to generate a low-speed signal having a lower frequency than the oscillation signal; a detection circuit configured to detect a difference between a predetermined reference timing and a timing at which the low-speed signal has changed; a selection unit configured to select the oscillation signal so that the phase difference with respect to the reference signal is close to the detected difference; and an output unit configured to output the generated low-speed signal in synchronization with the selected oscillation signal.

Signal generation circuit and electronic apparatus

An analog-to-digital conversion device includes a plurality of counting period supply units that supply a period of length according to a voltage of an analog signal inputted into each counting period supply unit based on the voltage of the analog signal as a counting period, a plurality of counter circuits which are connected to a common power supply and which perform a counting operation that counts a count value in the counting period different from each other and generate a digital signal indicating the count value, and a plurality of compensation circuits which are connected to the power supply and which operate so that the greater the number of counter circuits that stop the counting operation among the plurality of counter circuits, the greater the number of the compensation circuits that operate.

Analog-to-digital conversion device

A clock tree unit cell circuit includes a first input terminal configured to receive a clock signal from an upstream side of a clock tree; a first output terminal configured to output a clock signal to a downstream side of the clock tree; a second input terminal configured to receive a standby signal from the upstream side of the clock tree; a third input terminal configured to receive a standby signal from the downstream side of the clock tree; a logic circuit configured to perform a predetermined logical operation on the clock signal inputted to the first input terminal and output the clock signal to the first output terminal; and a control circuit that is connected to the second input terminal, the third input terminal, and an output control terminal of the logic circuit.

Growing community of inventors

Kanagawa, Japan

Yasunori Tsukuda