National Institute of Advanced Industrial Science and Technology

Duaxes Corporation

Bits Co., Ltd.

Yasunori Terashima

Mitsugu Nagoya

Kenji Toda

Toshihiro Katashita

Kazumi Sakamaki

Takeshi Inui

Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized. In order to avoid the hash values of different packets from having a same value, the hash function is configured so as to avoid that the same hash value is given to different packets or, when packet values have a common hash value, the packet is re-shaped into a packet having a different hash value.

FPGA-based network device testing equipment for high load testing

Growing community of inventors

Shinagawa-ku, Japan

Yasunori Terashima