Oki Electric Industry Co., Ltd.

Subaru Corporation

Yasunori Sato

Kei Suzuki

Hiroshi Fujisawa

Yoshio Sakata

Masato Ogura

Takahiro Maeno

Shosaku Tsukagoshi

A switch simulation device attachable to a touch panel includes a volume switch including a main body having first and second contact points, a head rotatable around a central axis of the main body and movable in the central axis direction, and an internal opening-and-closing unit electrically coupling and uncoupling the first and second contact points in response to movement of the head in the central axis direction, an operation member including a conductive material and coupled to the head to be rotatable and movable integrally with the head, a contact terminal that includes a conductive material, and is electrically coupled to the first contact point and in continuous contact with the operation member regardless of rotation and movement of the operation member, and a first coupler that electrically couples a first region of the touch panel to the second contact point.

Switch simulation device

A lightning current controlling method includes adjusting surface roughness of a surface of an aircraft body of an aircraft, a charged amount of the surface of the aircraft body of the aircraft, or both, to cause a passing path of a lightning current to be controlled when the aircraft is struck by lightning.

Lightning current controlling device, lightning current controlling method, and aircraft

A video signal detecting circuit includes a synchronization detector for detecting a vertical synchronous signal in an input video signal. A counter starts counting pixel clock pulses in response to every vertical synchronous signal thus detected, and outputs a first signal when the count of pixel clock pulses reaches a preselected value. A comparator compares the vertical synchronous signal detected with the first signal for outputting a second signal representative of a difference between them. A mean circuit produces a mean value of the second signals over a plurality of pictures of the input video signal. An adjusting circuit adjusts the vertical synchronous signal with the mean value to output the resultant adjusted signal as a vertical synchronous signal. The preselected number is substantially equal to the standard number of pixels included in a single picture.

Video signal detecting circuit for adjusting sync signals with a mean difference of the number of pixels from a standard

A memory device comprises a differential circuit for outputting a signal corresponding to the difference in value between an input read address signal and an input write address signal, a determination circuit for outputting a decision signal responsive to the output of the differential circuit and an address generating circuit for outputting a generated write address and a generated read address having a given or greater difference in signal value therebetween, based on the input read address signal, the input write address signal and the decision signal.

Memory device and method of controlling the same

A memory circuit includes an input selector for receiving input data serially at an interval of a period T and outputting the input data and an address counter for generating first address data sequentially at an interval of a having period 2T and second address data sequentially at an interval having period 2T. The second address data is delayed a period T from the first address data. The memory circuit of the present invention further includes two memory blocks coupled to the input selector and address counter. One memory block stores even numbered input data in response to the first address data and outputs them at the interval of the period 2T. The other memory block stores odd numbered input data in response to the second address data and outputs them at the interval of the period 2T.

Memory circuit for alternately accessing data within a period of address

A scrambling/descrambling apparatus has a data memory for storing a data word, a bit invert flag, and numerical data. A bit shift operating section performs, on receiving a bit of data to be outputted or a bit of input data, a bit shift operation with that bit and stores resultant data in the data memory in the form of a first data word. A randomizing/derandomizing section randomizes or derandomizes the input data by using the first data word and based on a generating polynomial and, depending on a state represented by the bit invert flag, inverts the bit of the data to be outputted to develop output data. A count processing section increments or decrements the numerical value stored in the data memory and, depending on the numerical value, selectively sets the bit invert flag to a predetermined state. A count controlling section replaces the numerical value with a predetermined initial value on the basis of the first data word and bit invert flag. The data memory holds a second and a third data word, bits of which corresponding in position to a particular bit of the first data word are a ZERO and a ONE, respectively. The count controlling section reads selectively either one of the second and third data words out of the data memory depending on the value of the bit which is inputted to the bit shift operating section, Exclusive-ORs the data word read out and the first data word, performs a masking operation with a data word resulting from the Exclusive-ORing for validating a bit corresponding in position to the particular bit position of the first data word while invalidating the remaining bits, and replaces the numerical value with the initial value when a data word resulting from the masking operation is indicative of a ZERO or when the bit invert flag is in the predetermined state. Alternatively, the count controlling section may read the first data word out of the data memory and, depending on the value of the bit which is inputted to the bit shift operating section, NOT or transfer the first data word, performs a masking operation with a data word representative of a result of NOTing or that of transfer for validating a bit corresponding in position to the particular bit position of the first data word while invalidating the remaining bits, and replace the numerical value with the initial value when a data word resulting from the masking operation is indicative of a ZERO or when the bit invert flag is in the predetermined state.

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Tokyo, Japan

Yasunori Sato