Nippon Gakki Seizo Kabushiki Kaisha

Yasunori Mochida

Terumoto Nonaka

Jun-ichi Nishizawa

Tadahiko Hotta

Takashi Yoshida

Osamu Hanagasaki

Akinori Endo

Shin Yamashita

Hirokazu Katoh

A semiconductor integrated logic circuit comprises a load transistor having a carrier injecting region and a carrier extracting region and an inverter transistor having a source region, drain regions, channel regions each connected between the source region and each of the drain regions, and gate regions defining the respective channel regions therebetween. The extracting region is merged into the gate regions. The channel regions have such dimensions and an impurity concentration that the channels are closed with depletion layers extending from the gate regions at zero gate voltage. The gate regions constitute a logic input and the drains constitute logic outputs. The zero gate voltage renders the channels non-conductive and the raised voltage renders the channels conductive, thus realizing an inverter circuit useful for wired logics.

Multi-drain enhancement JFET logic (SITL) with complementary MOSFET load

A reference frequency generator for a tuning apparatus comprising a variable frequency divider which frequency divides a source signal in accordance with frequency division data stored in one or more ROM's. The frequency division data comprises note data for specifying frequencies of respective notes in one octave of a musical scale, pitch deviation data for specifying pitch deviation of the respective notes in one octave with respect to the frequencies specified by said note data and tuning curve data for specifying tuning characeristics covering several octaves, so that the generator generates reference frequency signals representing various pitch deviations and tuning characteristics as well as a standard tuning pitch or characteristic.

Reference frequency signal generator for tuning apparatus

In a semiconductor device of the type arranged so that the minority carriers are injected into a lightly-doped n type semiconductor layer from a heavily-doped p type semiconductor layer provided in the n type layer, that portion of the p type layer excluding a certain portion is separated from the n type layer by a separator layer to cause the p type layer to contact the n type layer only at the certain portion, whereby the carrier injection is restricted to occur within a limited region of the n type layer contacting the certain portion of the p type layer. The separator and the p type layer are formed, by relying on a self-alignment technique using a double-mask layer, as diffused regions partially overlapping each other with a good relative alignment in the n type layer.

Semiconductor device and manufacturing process thereof

A compound transistor circuitry comprises a non-saturation type first field effect transistor and a saturation type second field effect transistor which is direct-coupled to the source circuit of said first FET. The internal dynamic resistance of the second FET functions as a negative feed-back element for the first FET. This internal dynamic resistance will greatly increase when the drain current of the second FET saturates. As a result, the compound transistor circuitry presents an output characteristic closely resembling that of the first FET within the operative range where the second FET does not saturate, whereas the circuitry presents an output characteristic that the current saturates at a level substantially equal to the saturating current of the second FET within the operative range where the second FET saturates.

Compound transistor circuitry

An automatic performance system in an electronic musical instrument comprises circuits for forming digital performance information signals by converting the displacement of movable members operated according to the contents of a performance into digital signals, and circuits for forming musical tone information signals corresponding to the contents of the performance from harmonic rich tone signals by controlling predetermined signal paths with electronic switches operated in response to the performance information signals, the digital performance information signals being detected and stored, and read out into the electronic switches at proper time instants, whereby all of the performance information signals are automatically reproduced as musical tone information signals with fidelity. The digital performance information can be automatically modified as desired in the process of storage and reproduction thereof to obtain modified musical tone information, and can furthermore be stored as information in a compressed state which contains digital signals indicating the occurrence of events in the performance and relative time information between the events.

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Hamamatsu, Japan

Yasunori Mochida