Kabushiki Kaisha Toshiba

Toshiba Infrastructure Systems & Solutions Corporation

Yasunori Maki

Hiroshi Sukegawa

Hideki Ogawa

Daisuke Yamamoto

Takafumi Sonoura

Takashi Inagaki

Seiji Tokura

Takeshi Takamiya

Yusuke Ito

Hideto Yui

Akihiro Mori

Nobuyuki Kishi

An SD memory card host controller supplies a clock to an SD memory card and issues a read command. After that, the host controller stops supplying the clock to the SD memory card during latency of read data from receipt of a response to the read command from the SD memory card to readout of data. The host controller resumes supplying the clock immediately before a data cycle starts. Power savings can thus be achieved by controlling the clock to be supplied to the SD memory card.

Method and apparatus of clock control associated with read latency for a card device

A NAND bus interface independently receives 16 ready/busy signals from 16 flash EEPROM chips and thereby separately manages the operating states of these flash EEPROMs. Once a flash EEPROM as a write access target is set in a ready state, a write access to this write access target flash EEPROM is started without waiting for completion of the operations of all the flash EEPROMs. Each flash EEPROM is of a command control type capable of automatically executing a write operation. This allows parallel processing of the flash EEPROMs, i.e., a write access to a given EEPROM can be performed while a data write to another flash EEPROM is being executed. An ECC calculating circuit calculates a data string transferred in units of 256 bytes from a data buffer by a processor, and generates an ECC corresponding to that data string. The 256-byte data string is added with the generated ECC and transferred to a data register of a flash EEPROM. Even if abnormal cells are produced at the same bit position in a plurality of pages of a flash EEPROM, only one abnormal cell is contained in a data string as an object of the ECC calculation. This makes it possible to perform error detection and correction by a common simple ECC calculation without using any complicated ECC arithmetic expression with a high data recovery capability.

Semiconductor disk system having a plurality of flash memories

Growing community of inventors

Hamura, Japan

Yasunori Maki