Seiko Epson Corporation

Yasunori Koide

Takashi Toya

Mitsutoshi Miyasaka

Tetsuji Fujita

Yuiga Hamade

Hiroyoshi Ozeki

Yasuhiko Murakami

A technique for realizing energy saving. According to a biological information acquisition device, light emitting power per unit area of one light emitting element emitting light when first biological information is acquired is weaker than light emitting power per unit area of one light emitting element emitting light when second biological information is acquired.

Biological information acquisition device and biological information acquisition method

A technique restrains degradation of a light emitting element. A biological information acquisition device acquires light receiving result by causing a light receiving unit to receive light emitted by a light emitting unit serving as a measurement-purpose light emitting unit, and acquires biological information by using the light receiving result. The light is emitted from the light emitting unit so as to acquire the light receiving result for one time, while a plurality of light emitting patterns are switched between a light emitting element which emits the light and a light emitting element which does not emit the light in a plurality of the light emitting elements.

A biological information acquisition device includes: a light emitting unit which casts light on a living body; a plurality of light receiving units which receives the light transmitted through the living body; and a control unit which controls the light emitting unit and the light receiving units. The control unit causes the light emitting unit to emit light as a measurement light emitting unit, causes a plurality of measurement light receiving units spaced apart from the measurement light emitting unit by a first distance, of the plurality of light receiving units, to receive the light cast from measurement light emitting unit and thus acquires a plurality of light receiving results, and acquires biological information using a first light receiving result with a highest light reception intensity and a second light receiving result with a lowest light reception intensity, of the plurality of light receiving results.

An imaging device includes a photodiode having a first electrode and a second electrode, a first transistor that controls electrical connection between the first electrode and a first wiring line through which first voltage is supplied, and a second transistor that controls electrical connection between the first electrode and a second wiring line through which second voltage different from the first voltage is supplied, and voltage at the second electrode is read with the first transistor and the second transistor turned off.

Imaging device, electronic apparatus, and imaging method

An imaging apparatus includes a plurality of unit circuits connected to a detection line, and a signal output circuit. Each of the plurality of unit circuits includes a light receiving device including an electrode connected to a wire and an electrode, and a transistor that controls electrical connection between the electrode and the detection line. The signal output circuit includes a light receiving device in a light-blocking state including an electrode connected to a wire and an electrode, and a detection circuit that outputs a detection signal according to a potential of a detection point between the electrode and the electrode when the light receiving device and the light receiving device are in a reverse bias state between the wire and the wire.

Imaging apparatus and electronic apparatus

An infrared detection circuit includes a charge transferring transistor, a gate control circuit and a negative potential generating circuit. The charge transferring transistor is disposed between a read node configured to be connected to one end of an infrared detection element and a tank node to transfer an electric charge from the infrared detection element to the tank node. The gate control circuit is connected to a gate of the charge transferring transistor. The negative potential generating circuit is connected to the tank node to set the tank node to a negative electric potential when the charge transferring transistor transfers the electric charge.

Infrared detection circuit, sensor device, and electronic instrument

A ferroelectric memory includes a memory cell array including a first unit block, a second unit block, and a plurality of dummy cells. The plurality of dummy cells being arranged toward a column direction and being disposed between the first unit block and the second unit block. The first unit block including a plurality of first memory cells arranging in t rows, and including a plurality of first plate lines arranging toward a row direction. The second unit block including a plurality of second memory cells arranged in t rows, and including a plurality of second plate lines arranging toward a row direction. Each of the plurality of dummy cells including a ferroelectric capacitor. Either of the first second plate line or the second plate line of the second unit block extending above the plurality of dummy cells.

Semiconductor memory device and electronic apparatus

A ferroelectric memory device includes: a memory cell having a ferroelectric capacitor connected between a plate line and a bit line; a first node connected to the bit line through a charge transfer MISFET; a potential generation circuit that has a first capacitor having a first terminal connected to the first node and a first switching MISFET connected to a second terminal of the first capacitor, and is capable of setting the first node to a negative potential; and a sense amplifier connected to the second terminal of the first capacitor. When reading a charge stored in the ferroelectric capacitor, the potential generation circuit sets the first node at a negative potential and then sets the first switching MISFET to an off state, thereby setting the second terminal of the first capacitor to a floating state, and the sense amplifier amplifies a potential on the second terminal of the first capacitor in the floating state.

Ferroelectric memory device, method for driving ferroelectric memory device, and electronic equipment

A ferroelectric memory device includes: a memory cell having a transistor and a ferroelectric capacitor connected in series between a bit line and a plate line, and a connecting section below the ferroelectric capacitor; a dummy cell having a transistor, a ferroelectric capacitor and a connecting section, wherein the dummy cell has an electrically disconnected section among the bit line, the transistor, the ferroelectric capacitor, the connecting section and the plate line.

Ferroelectric memory device and electronic apparatus

A ferroelectric memory device includes: a first p-channel type MISFET connected between a first bit line and a first node; a second p-channel type MISFET connected between a second bit line and a second node; a first negative potential generation circuit connected to the first node; and a second negative potential generation circuit connected to the second node, wherein a gate terminal of the first p-channel type MISFET and the second node are connected to each other, and a gate terminal of the second p-channel type MISFET and the first node are connected to each other.

A ferroelectric memory device, having: a first charge-transfer MISFET, connected between a first bit line and a first node; a second charge-transfer MISFET, connected between a second bit line and a second node; a first capacitance, connected to the first node; a second capacitance, connected to the second node; a first p-channel MISFET, connected between the first charge-transfer MISFET and the first node, and the gate electrode of which is connected to the second node; and a second p-channel MISFET, connected between the second charge-transfer MISFET and the second node, and the gate electrode of which is connected to the first node.

Ferroelectric memory device and electronic equipment

A semiconductor memory device having: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; two or more third wirings connecting the third terminals of the m memory cells, and means for selecting a third wiring from among the third wirings, the third wiring being selected based on the result of calculation in an adder circuit and a subtractor circuit.

A ferroelectric memory device includes memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines. The ferroelectric memory device includes: first and second local bit lines associated with a first main bit line; first and second connection transistors for connecting the first and second local bit lines to the first main bit line; first and second grounding transistors for grounding the first and second local bit lines; a first selection line that is commonly connected to gates of the first grounding transistor and the second connection transistor; and a second selection line that is commonly connected to gates of the first connection transistor and the second grounding transistor.

Ferroelectric memory device

A ferroelectric memory device being short in the bit line direction. The ferroelectric memory device is structured including a first word line extending in the first direction; a plurality of element regions arrayed in the first direction on both sides of the first word line; a plurality of ferroelectric capacitors connected to the respective element regions and driven by the first word line. Each of the element regions preferably has a stair-like shape when seen in a plane view and the first word line is preferably arranged bent between the element regions.

Growing community of inventors

Matsumoto, Japan

Yasunori Koide