Seiko Epson Corporation

Yasunobu Tokuda

Takashi Kumagai

Masahiro Takeuchi

Koji Miyashita

Hiroshi Kayamoto

A drive circuit includes an output circuit having an output node that outputs, to a charge pump circuit, a drive clock signal for driving the charge pump circuit. The output circuit generates the drive clock signal based on a first clock signal and a second clock signal that is a signal whose voltage level does not change in a period during which the voltage level of the first clock signal changes, and controls, based on the second clock signal, an impedance of the output node so as to be up, in a period before the voltage levels of the drive clock signal changes.

Drive circuit, integrated circuit device, and method for controlling charge pump circuit

A latch circuit that latches stored data of a nonvolatile storage device used for setting the function of a semiconductor device and adjusting the characteristics of the semiconductor device required a dedicated input-output circuit for a test of the semiconductor device. By providing a dummy storage device, it becomes possible to perform a test of the semiconductor device without providing a dedicated input-output circuit.

Nonvolatile storage device, integrated circuit device, and electronic apparatus

Output circuit and electronic apparatus using the same

Semiconductor memory device and a method for stepping up its word lines

A first word line connects the gate electrodes of first transfer transistors in adjacent memory cells. A second word line connects the gate electrodes of second transfer transistors in adjacent memory cells. A ground line connects the source regions of first and second driver transistors. The first and second word lines and ground line are formed by a wiring layer different from the wiring layer that forms the gate electrodes of the first and second transfer transistors. The ground line shields the first and second driver transistors, TFTs and the like. Drain contacts include chamfered sides between which the ground line is disposed.

Semiconductor static random access memory device

Semiconductor memory device

A semiconductor memory adapted to receive a chip selection signal and address signal, composed of: a signal generating circuit for generating inner selection signals with respect to the chip selection signal, a pulse generating circuit for detecting any changes in the address signals and generating a pulse signal; and a pulse width changing circuit for inputting the pulse signal to output a control signal for precharging or equalizing the data lines of a memory cell array. The pulse width changing circuit outputs the control signal having a pulse whose pulse width corresponds to what is obtained by converting the pulse width of the pulse signal into a longer one when the inner selection signals are in the chip-selecting condition.

Growing community of inventors

Okaya, Japan

Yasunobu Tokuda