Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Yasunobu Nakase

Naoya Watanabe

Yoshikazu Morooka

Tsutomu Yoshimura

Tetsuya Watanabe

Koji Nii

Kimio Ueda

Chikayoshi Morishima

Niichi Itoh

Hiroshi Makino

Hiromi Notani

Harufusa Kondoh

Kenji Anami

Jingo Nakanishi

A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply. The semiconductor integrated circuit device includes a level shifterand two capacitors Nand C. The level shifterreceives an input signal and converts the received signal to a signal having a voltage amplitude greater than that of the received signal, then to provide the signal to a node D. The capacitor Nis connected to the node D, and the capacitor Cis connected in series with the capacitor N. The capacitor Nis formed of a MOS transistor having a gate connected to the node Dand a source and a drain both connected to the capacitor C

Semiconductor integrated circuit device including a level shifter

A local sense amplifier drives a global bit line pair by potentials of data storage nodes when a global word line attains an H level. A global sense amplifier amplifies the potential difference of data storage nodes when a global sense enable signal attains an H level. The global sense enable signal is inverted by an inverter to be provided to a global word driver. When the global word line attains an L level by the global word driver, the local sense amplifier suppresses the drive of the global bit line pair.

Semiconductor memory device having potential amplitude of global bit line pair restricted to partial swing

Core circuitry is configured with a transistor formed of a gate oxide film of a thin film thickness, receiving a first power supply voltage to operate. Interface circuitry is configured with a transistor formed of a gate oxide film of a thick film thickness, receiving a second power supply voltage to operate. An appropriate voltage is supplied to the substrate of a P channel MOS transistor and an N channel MOS transistor which are output drivers, based on a mode select signal set according to the voltage level of the second power supply voltage, whereby a PNP parasitic bipolar transistor and an NPN parasitic bipolar transistor are driven at high speed. Although the interface circuitry of a semiconductor device is configured with a transistor formed of a thick gate oxide film, the speed will not be degraded even if the power supply voltage is set at a low voltage level.

Semiconductor device with interface circuitry having operating speed during low voltage mode improved

In a bus circuit which includes a plurality of signal lines, insertion pattern &agr;, which provides repeaters in only an odd numbered series of signal lines, and insertion pattern &bgr;, of which the segment length is equal to that of pattern &agr; and which provides repeaters to only an even numbered series of signal lines, are arranged in an alternating manner in accordance with the length of the signal lines. As a result, the segments during which data signals on the neighboring signal lines run together in opposite phases become half the entire length of the signal lines. Therefore, this bus circuit can prevent the operational speed from becoming slowed.

Bus circuit preventing delay of the operational speed and design method thereof

Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.

Semiconductor memory device capable of generating internal data read timing precisely

Even if a power supply potential VDD of a core section is set in an off state, a latch of a level conversion circuit holds a value corresponding to an output. It is, therefore, possible for a semiconductor device to hold an output state of an output node. Thereafter, an enable signal is deactivated, whereby the output node can be set in a high impedance state and a bus or the like can be released to the other device.

Semiconductor device capable of maintaining output signal even if internal power supply potential is turned off

The dummy cell of the SRAM corresponds to a normal memory cell of which first and second P-channel MOS transistors for loading are replaced by the first and the second N-channel MOS transistors, of which gate and source are provided with power supply potential and ground potential, respectively. When a word line rises to &ldquo;H&rdquo; level, third and fourth N-channel MOS transistors for accessing are rendered conductive, to pass current from dummy bit line to a line of ground potential via the third N-channel MOS transistor, the first N-channel MOS transistor, and a fifth N-channel MOS transistor for driving. Accordingly, speed of potential decrease of the dummy bit line may be faster than that of bit line. Hence, operational timing can easily be optimized, and operational margin can be increased.

Static type semiconductor memory device with dummy memory cell

Dummy cells each having the same layout as a normal memory cell are aligned in a row direction to the normal memory cells, and are arranged in rows and columns. In each dummy cell column, a dummy bit line is arranged, and a plurality of dummy cells are simultaneously selected and connected to the corresponding dummy bit line when one word line is selected. A voltage detecting circuit detects the potentials on the dummy bit lines to determine timing of activation of a sense amplifier. In the semiconductor memory device, the potential on the dummy bit line can be changed at high speed, and internal data read timing can be optimized independent of a structure of a memory cell array.

Semiconductor memory device with internal data reading timing set precisely

A circuit module includes a connector terminal ( A) provided on a front surface of a printed wiring board ( ) and connected to a data pin (DQ ) of a memory IC ( ) through an interconnect line ( ). A conductive connector terminal ( ) corresponds to the connector terminal ( ) and is provided on a back surface of the printed wiring board ( ). A through hole ( ) extends between part of the front surface of the printed wiring board ( ) where the connector terminal ( ) is formed and part of the back surface thereof where the conductive connector terminal ( ) is formed. A conductor fills the through hole ( ), thereby suppressing skews resulting from a difference in interconnect line length on the circuit module and decreasing a stub capacitance to achieve the reduction in power consumption.

Circuit module

Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions,to,and,to,and polysilicon regions,to,) of a memory cell for one memory cell unit of a memory cell array region,is identical to that of a dummy cell of a peripheral dummy cell region,and both patterns present a line symmetrical relationship with respect to a boundary line BC,In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region,is identical to that of a dummy cell of a power wiring region,and both patterns present a line symmetrical relationship with respect to a boundary line BC

Semiconductor device

A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.

Semiconductor memory device permitting time required for writing data to be reduced

In a PLL circuit including a plurality of VCOs, first and second switches are respectively connected between the gate and source and the gate and drain of a P channel MOS transistor included in a current mirror circuit of each VCO. In a VCO which is employed, only the second switch is turned on to allow a control current to flow. In a VCO which is not employed, only the first switch is turned on to cut off the control current. Compared with a conventional circuit in which all of the plurality of VCOs are always producing oscillations, the power consumption is reduced.

Phase-locked loop circuit and voltage-controlled oscillator capable of producing oscillations in a plurality of frequency ranges

Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is 'H'. On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is 'L'. When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained. With this configuration provided is a 90-degree phase shifter which achieves the uniform input load to improve a phase offset.

Ninety-degree phase shifter

Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.

In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to 'L' level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.

Growing community of inventors

Hyogo, Japan

Yasunobu Nakase