Renesas Electronics Corporation

Other

Renesas Technology Corp.

Yasunobu Aoki

Masamichi Fujito

Takahiro Yokoyama

Makoto Mizuno

Takashi Kurafuji

Takashi Iwase

Yuji Uji

Tomohiro Uchiyama

Shuichi Sato

Kenji Kawada

Kazuhiko Kajigaya

Hiroki Fujisawa

Osamu Nagashima

Seiji Narui

Shinichi Miyatake

Masatoshi Hasegawa

Tsuyuki Suzuki

Tsutom Takahashi

Kazumasa Yanagisawa

Toshiyuki Mine

Kan Yasui

Toshio Sasaki

Yuji Tanaka

Yasuhiro Shimamoto

Tetsuya Ishimaru

Yoshihiko Yasu

Koichi Toba

Hideo Kasai

Yasuto Igarashi

Mariko Ohtsuka

Junpei Inoue

Toshiaki Takahira

To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device. In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.

Data processing semiconductor device

The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.

Semiconductor device

A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N&#x2014;H bonds and Si&#x2014;H bonds contained in the silicon nitride film SIN is made to be 5&#xd7;10cmor less.

Nonvolatile semiconductor memory device

There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.

Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device

A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.

Semiconductor integrated circuit device having an improved operation control for a dynamic memory

Dynamic RAM, semiconductor storage device, and semiconductor integrated circuit device

Growing community of inventors

Tokyo, Japan

Yasunobu Aoki