Hitachi-high-technologies Corporation

Canon Kabushiki Kaisha

Hitachi, Ltd.

Adv Antest Corporation

Yasunari Souda

Yuji Takagi

Haruo Yoda

Shinichi Hashimoto

Yasutaka Toyoda

Hiroya Ohta

Yoshikiyo Yui

Koji Arai

Muneyuki Fukuda

Osamu Nasu

Sayaka Tanimoto

Hiromasa Yamanashi

A pattern data examination method and system capable of accurately and speedily examining a circuit pattern without failing to extract pattern contour data are provided. While pattern comparison is ordinarily made by using a secondary electron image, a contour of a pattern element is extracted by using a backscattered electron image said to be suitable for observation and examination of a three dimensional configuration of a pattern element, and pattern inspection is executed by using the extracted contour of the pattern element. More specifically, pattern inspection is executed by comparing a contour of a pattern element with design data such as CAD data to measure a difference between the contour and the data, and by computing, for example, the size of the circuit pattern element from the contour of a pattern. From two or more backscattered electron images formed by detecting backscattered electrons at two or more different spatial positions, pattern contour data contained in the backscattered electron images may be obtained.

Pattern inspection method and pattern inspection system

Potentials at a plurality of points on a diameter of a semiconductor waferare measured actually. Then, a potential distribution on the diameter is obtained by spline interpolation of potentials between the actually-measured points adjacent in the diameter direction. Thereafter, a two-dimensional interpolation function regarding a potential distribution in the semiconductor waferis obtained by spline interpolation of potentials between points adjacent in the circumferential direction around the center of the semiconductor wafer. Then, a potential at a observation point on the semiconductor waferis obtained by substituting the coordinate value of this observation point into the two-dimensional interpolation function. As a result, a potential distribution due to electrification of the wafer can be estimated accurately, and the retarding potential can be set to a suitable value.

Charged particle beam apparatus and control method therefor

A multi-electron beam exposure method and apparatus, wherein electron beams are applied to a sample surface mounted on a traveling sample stage to perform repeated exposure of chip patterns. An exposure region of the sample surface is partitioned into multiple stripe regions having a width in an x-axis direction, and each of the multiple stripe regions is further partitioned into multiple main fields having a width in a y-axis direction. At least one of the widths of the main fields in the x- and y-axis directions is set to a value, and exposure pattern data for one chip based on the partitioned main fields is stored as a unit. The stored exposure pattern data is readout a number of times corresponding to the number of chips repeatedly, and each electron beam provides repeated exposure of same regions of the chips.

Multi-electron beam exposure method and apparatus

The dimension of the main field as a unit region for exposure is set to an integral submultiple of the arrangement pitch of the LSI to be exposed, by the control computer, and the exposure data stored in the form associated with electron beams from a data generation circuitis limited to one-chip data alone in units of a stripe. This data is repeatedly read out to write the stripe. Further, a storage circuitis provided to store the exposure data by means of a double buffer memory unit for each electron beam. While LSI is written according to one of the buffers, the next exposure stripe data is prepared on the other buffer, thereby bringing about a substantial reduction in the required speed of the exposure data generation circuit.

Growing community of inventors

Kawasaki, Japan

Yasunari Souda