International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Yasunao Katayama

Daiju Nakano

Kohji Takano

Atsuya Okazaki

Nobuyuki Ohba

Sumio Morioka

Yasuteru Kohda

Toshiyuki Yamane

Seiji Munetoh

Wei Hwang

Nicholas C M Fuller

Arun Sridhar Natarajan

Yasushi Negishi

Tadayuki Okada

Rajiv V Joshi

Toshiaki Kirihata

Stephen Victor Kosonocky

Dennis Merton Newns

Wing Kin Luk

Chang Chyi Tsuei

Shigenori Shimizu

Dennis M Newns

Roy L Scheuerlein

Seiji Muneto

Akashi Sato

Naoya Kuse

Atsuya Okaza-Ki

Methods and systems for neural network processing include configuring a physical network topology for a network that includes hardware nodes in accordance with a neural network topology, one of which is designated as a master node with any other nodes in the network being designated as slave nodes. One or more virtual neurons are configured at each of the hardware nodes by the master node to create a neural network having the neural network topology. Each virtual neuron has a neuron function and logical network connection information that establishes weighted connections between different virtual neurons. A neural network processing function is executed using the neural network.

Dynamically reconfigurable networked virtual neurons for neural network processing

A neural network processing system includes one source node having a source memory and a source core, and one destination node having a destination memory and a destination core, the source core and the destination core being von-Neumann cores, the destination memory including weight data storage areas for storing weight data corresponding to each node, an accumulation memory for accumulating the weight data, and an event address memory, the destination core identifying the weight data storage area and accumulating the weight data to store the accumulated weight data in the accumulation memory, the source memory including a data set having first information for identifying the destination node and second information for identifying the weight data storage area, and the source core reading the data set and sending the second information in the data set to the destination node to conduct remote memory write.

Neural network processing with von-Neumann cores

A computer-implemented method is provided for exclusive control of shared memory objects. The method computer-implemented includes transmitting and performing a plurality of accesses to the shared memory objects from local and remote locations via read requests and write requests made to a memory, and controlling the read and write requests by a memory controller including a read queue, a write queue, and a lock address list. The computer-implemented method further includes initiating each read request to the memory via the memory controller whatever the corresponding lock bit is, initiating each write request to the memory from the recently read location via the memory controller when the corresponding lock bit is enabled, otherwise notify the requesting local or remote locations as incomplete, and enabling and disabling the corresponding lock bit after the initiation of the read and write requests to the memory, respectively.

Low overhead exclusive control for shared memory objects

A memory controller is provided for accessing shared memory objects by read and write requests made to a memory. The memory controller includes a list for registering address locations of the shared objects in the memory, and having slots for a lock bit. The memory controller includes a read wait queue and a write wait queue for selectively inputting, outputting, holding, and purging requests. The memory controller includes a read initiated queue and a write initiated queue for selectively inputting and purging requests transferred from the read wait queue and the write wait queue, respectively, upon memory access initiation and completion. The memory controller includes a controller for controlling the wait queues using policies by determining which requests to output, hold, and purge, based on a list entry, a lock bit and TTL information set to each request upon a hold being applied thereto and decremented in each cycle.

Queue control for shared memory access

Methods and systems for memory-side shared caching include determining whether a requested memory access is directed to shared portion of memory by referencing a lock address list in a memory controller. If the requested memory access is for the shared portion of memory, it is determined whether an associated data object is present in a memory-side cache. If the associated data object is present in the memory-side cache, the memory-side cache is accessed. If the associated data object is not present in the memory-side cache, an external memory is accessed.

Memory-side caching for shared memory objects

A computer-implemented method is provided for enabling exactly-once messaging. The computer-implemented method includes transmitting a plurality of messages from a first location to a second location via read requests and write requests made to a memory and controlling the read and write requests by a memory controller including a read queue, a write queue, and a lock address list, each slot of the lock address list associated with a lock bit. The computer-implemented method further includes initiating the read requests from the memory via the memory controller when associated lock bits are enabled and initiating the write requests from the memory via the memory controller when associated lock bits are disabled. The computer-implemented method further includes enabling and disabling the lock bits after the initiation of the write and read requests, respectively.

Memory access for exactly-once messaging

Embodiments include providing content requested by a user via an access point capable of wireless communication. Aspects include receiving the content provided by the management server and storing the content provided by the management server into a volatile memory provided in the wireless communication apparatus. Aspects also include storing difference data into a nonvolatile memory if it is requested to change the content stored in the volatile memory and monitoring a state of communication connection with the access point and whether or not a packet giving an instruction to hold the content has been received. Aspects further include deleting the content stored in the volatile memory if communication with the access point is disconnected or if the packet is unreceived.

Information processing system, wireless communication apparatus, method and program

A processor issues a command to a memory through an electrical memory link and performs a process according to the command through the electrical memory link. The processor issues a routing command to an optical circuit switch (OCS) through an OCS control line. In response to the routing command, the OCS establishes a routing of an optical memory link from the processor to the BDM. In response to the establishment of the optical memory link from the processor to the BDM, the processor (or a BDM (internal/dedicated) controller) switches from performing the process through the electrical memory link to performing a process through the optical memory link (continuously without an interruption between the successive processes). Corresponding systems are also disclosed herein.

Electrical and optical memory access

Transmitting device, receiving device, communication device, programs, transmission method, and receiving method for wireless communication of continuous data in the form of packets. A transmitting device includes a data receiving unit that receives continuous data from a network, the continuous data including actual data and null data; a packetizing unit that deletes at least a part of the null data from the continuous data to generate a packet for wireless communication; a transmitting unit that modulates the packet into a radio carrier wave and wirelessly transmits the resulting packet; and a control unit that causes the transmitting unit to stop transmission of the radio carrier wave during at least a part of a time period in which no such packet is transmitted wirelessly.

Transmitting device, receiving device, communication device, programs, transmission method, and receiving method for wireless communication of continuous data in the form of packets

To provide a high-density optical interconnect device, information processing device and data transmission method which are able to suppress limitations caused by the widening of light beams and the size of lenses. An optical interconnect unit includes a plurality of first lenses and a plurality of second lenses corresponding to a plurality of light-emitting element groups, and a plurality of light beams emitted from the plurality of light-emitting element groups pass through plurality of first lenses and the plurality of second lenses. The optical interconnect unit also includes a plurality of third lenses and a plurality of fourth lenses, and light beam groups pass through any one of the plurality of third lenses and the plurality of fourth lenses, and are focused by any one of a plurality of light-receiving element groups that include a plurality of light-receiving elements.

Optical interconnect device, information processing device and data transmission method

A receptor of wireless signal in a wireless communication system can be configured to correct for degradations of signal quality. The reception apparatus can include a filter which is configured to create a filtered signal by make corrections to a reception signal which carries a symbol. Based on the created filtered signal, a symbol can be decided and weighted to evaluate the error of the original reception signal. Using the weighting information, a parameter of the filter can be updated to more accurately correct the reception signal.

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Tokyo, Japan

Yasunao Katayama