Fujitsu Corporation

Fujitsu Semiconductor Limited

Yasumoto Tomita

Hirotaka Tamura

Koichi Shirahata

Hisakatsu Yamaguchi

Kanae Nakagawa

Masaki Arai

Satoshi Kawahara

Toshihiko Mori

Masaya Kibune

Katsuhiro Yoda

Makiko Ito

Takashi Arakawa

Takuya Fukagai

Amir Haderbache

Kyosuke Maeda

A barrier synchronization circuit that performs barrier synchronization of a plurality of processes executed in parallel by a plurality of processing circuits, the barrier synchronization circuit includes a first determination circuit configured to determine whether the number of first processing circuits among the plurality of the processing circuits is equal to or greater than a first threshold value, the first processing circuits having completed the process, and an instruction circuit configured to instruct a second processing circuit among the plurality of the processing circuits to forcibly stop the process when it is determined that the number is equal to or greater than the first threshold value by the first determination circuit, the second processing circuit having not completed the process.

Barrier synchronization circuit, barrier synchronization method, and parallel information processing apparatus

An information processing method includes executing a first process of performing a non-linear analysis by iterating a linear analysis, and executing a second process of predicting a residual threshold to be used for determination of convergence of the linear analysis by a prediction model, based on a residual transition and calculation time for each iteration of the linear analysis obtained for each residual threshold using a plurality of experimental values by the first process. The information processing method further includes performing passage of data between the first process and the second process through an inter-process communication using a shared memory set in a memory.

Information processing method, and information processing apparatus

A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization. The parallel information processing apparatus includes: a completion information storage configured to store completion information, wherein the completion information includes information relating to completion of processing of an own apparatus and information relating to completion of processing of a lower information processing apparatus located in the tree structure; and a control circuit configured to, in response to a determination result indicating that a current status amounts to a given condition, instruct a specified information processing apparatus to forcibly suspend processing, the specified information processing apparatus being an apparatus that has not yet completed processing before all of the plurality of information processing apparatuses have completed the processing.

Barrier synchronization system and parallel information processing apparatus

An information processing apparatus includes a processor including a first operation circuit that executes a product-sum operation, a second operation circuit that executes a certain operation, and a resister. The processor executes a first operation including the certain operation in a first layer in a neural network. The processor executes the first operation by a second method of calculating the certain operation by the second operation circuit, in a case where second operation time necessary for the first operation when the certain operation is executed by the second operation circuit is less than memory transfer time. Or the processor executes the first operation by a first method of calculating the certain operation by an approximate calculation by the first operation circuit, in a case where first operation time necessary for the first operation when executed by the first method is less than the memory transfer time.

Information processing apparatus, neural network program, and processing method for neural network

An image recognition apparatus includes a processor including a plurality of arithmetic units; and a memory storing a plurality of data elements, each corresponding to one of candidate regions detected in an image and indicating a location and an evaluation value of the corresponding candidate region. The processor sorts the data elements by calculating in parallel, in reference to evaluation values, indexes each indicating a position of a corresponding one of the data elements in a sorted ordering and transferring in parallel, after the calculation of the indexes, the data elements based on the indexes. The processor selects part of the candidate regions based on the sorted ordering of the data elements.

Image recognition apparatus and image recognition method for sorting candidate regions detected in image

In an information processing apparatus, a calculation circuit calculates energy values representing total energies of Ising devices that are set up with different noise widths, where the Ising devices have equal conditions about neuron-to-neuron connections. An exchange control circuit exchanges output values of neurons or noise widths, between first and second Ising devices having adjacent noise widths. This exchange takes place with an exchange probability based on a difference in the energy values between the first Ising device and the second Ising device.

Information processing apparatus, Ising device, and method for controlling information processing apparatus

The arithmetic processing circuit includes a first layer configured to dispose a learning neural network to compute a coefficient to be set in a recognition neural network, configured to recognize input data by using the coefficient computed on a basis of a recognition result of the recognition neural network with for the input data serving as a reference for computing the coefficient and a recognition result serving as a reference for the input data serving as the reference. The circuit further includes a second layer configured to dispose the recognition neural network to recognize the input data by the coefficient computed by the learning neural network. The circuit still further includes a third layer disposed between the first layer and the second layer, and configured to dispose a memory connected to both of the learning neural network and the recognition neural network.

Arithmetic processing circuit and information processing apparatus

A clock control circuit includes: a first buffer that receives a first pair of input clocks of multi-phase clocks, buffers and outputs the first pair of input clocks; a second buffer that receives a second pair of input clocks of the multi-phase clocks, and is controllable to buffer and output the second pair of input clocks or to output a fixed level; and a frequency multiplier that performs a logical operation on an output of the first buffer and an output of the second buffer, and outputs a first pair of output clocks or a second pair of output clocks as an output clocks, the first pair of output clocks is based on a frequency which is obtained by multiplying frequencies of the multi-phase clocks, and the second pair of output clocks is based on the same frequencies as the multi-phase clocks.

Clock control circuit, receiver, and communication device

A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.

Clock distributor and electronic apparatus

A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.

Clock distributor and electronic device

To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient.

Receiving device and receiving method

Receiving device

A clock generation circuit includes: a first determination circuit that detects an input signal at a first phase position based on first frequency signal; a second determination circuit that detects the input signal at a second phase position based on second frequency signal; a phase detector that compares output of the first determination circuit and output of the second determination circuit; a first summing circuit which sums comparison result and first control signal; a second summing circuit which sums comparison result and second control signal; a first voltage controlled oscillation circuit which receives output of the first summing circuit and outputs the first frequency signal; a second voltage controlled oscillation circuit which received output of the second summing circuit and outputs the second frequency signal; and a phase adjustment circuit which generates first control signal and second control signal based on first frequency signal and second frequency signal.

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Kawasaki, Japan

Yasumoto Tomita