Hitachi, Ltd.

Other

Yasumichi Yasuda

Mutsuhiro Mori

Yasunori Nakano

Tomoyuki Tanaka

Hiromi Hosoya

Yutaka Misawa

Hiroyuki Ozawa

Kenichi Onda

Yasuo Matsuda

Norikazu Tokunaga

Naoki Sakurai

Shin Kimura

Takuzo Ogawa

Jin Onuki

Hiroaki Hachino

Yasuhiro Mochizuki

Hideo Kobayashi

Hideyuki Yagi

Toshiki Kurosu

A high voltage semiconductor device is provided with a p layer which forms a main pn-junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n&plus; layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n&plus; layers and reaching the surface of an n&minus; layer through an insulating film, the area of the field plates being not less than one half of the n&minus; surface. This arrangement is particularly effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is very effective in improving the reliability of a high voltage control unit.

Semiconductor device and power converter using same

A high voltage semiconductor device is provided with a p layer which forms a main pn-junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n+ layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers and reaching the surface of an n- layer through an insulating film, the area of the field plates being not less than one half of the n- surface. This arrangement is particularly effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is very effective in improving the reliability of a high voltage control unit.

A highly reliable semiconductor device having a planar junction, which comprises a main junction and a plurality of field limiting ring regions surrounding the main junction, and an electrically floating conductive layer to completely cover that part of the surface of an n.sup.- layer between the main junction and the nearest field limiting ring region thereto through an insulating layer to suppress influences by external factors such as charged particles, etc. In accordance with such a structured device, when a voltage for making the main junction into a reverse bias state is applied, the potential of the conductive layer becomes fixed to an intermediate potential between the main junction and the nearest field limiting ring region thereto and plays a role of shield effect. In fact, even if the device is incorporated into a resin-sealed package and subjected to reliability tests (high temperature DC reverse bias tests), the breakdown voltage is not changed at all. Also, rather than effecting a device in which the conductive layer is electrically floating, the conductive layer which covers an overlying area between the main junction and the nearest field limiting ring region thereto can be electrically connected to the nearest field limiting ring.

Semiconductor device having planar junction

A high voltage semiconductor device is provided with a p layer which forms a main pn- junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n+ layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers and reaching the surface of an n- layer through an insulating film, the area of the field plates being not less than one half of the n- surface. This arrangement is effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is vey effective in improving the reliabilty of a high voltage control unit.

The present invention is directed to a semiconductor device which can achieve high current density and which has a high reliability. In the insulated gate semiconductor device according to the present invention, a plurality of insulating gates are provided, with each two adjacent insulating gates being spaced from each other, the insulating gates being provided on a second semiconductor region of a first conductivity type. A first semiconductor region, of the same or different conductivity type from that of the second semiconductor region, extends from a surface of the second semiconductor region opposed to the surface thereof having the insulating gates thereon. A plurality of third semiconductor regions are provided in the second semiconductor region, between the insulating gates and aligned therewith, and two fourth semiconductor regions are provided extending into each of the third semiconductor regions, aligned with the sides of adjacent insulating gates. Electrodes are respectively provided in contact with the first semiconductor region and in contact with the third and fourth semiconductor regions, the electrode in contact with the third and fourth semiconductor regions contacting such regions in the space between adjacent insulating gates. By utilizing such aligned third and fourth semiconductor regions, an insulated gate semiconductor device which operates at high current densities can be fabricated at high accuracy, and such device will be less influenced by parasitic bipolar transistor effects.

Vertical insulated gate semiconductor device having high current density

A first power semiconductor device with a semiconductor base to which an emitter wire electrode is connected through an emitter bonding pad and a gate wire electrode is connected through a gate bonding pad, wherein the gate bonding pad comprises a silicon oxide film, a silicon crystal layer and a gate wiring electrode made of aluminum containing silicon which are successively formed on the semiconductor base, and the gate wire electrode is connected to the gate wiring electrode. A second power semiconductor device wherein the emitter bonding pad is an emitter wiring electrode made of aluminum containing silicon which is directly formed on the semiconductor base, and the emitter wire electrode is bonded to the emitter wiring electrode.

Power semiconductor device

The present invention relates to a semiconductor device having an n-type semiconductor region forming one of the main surfaces of a semiconductor substrate, with a plurality of p-type semiconductor regions formed in the n-type semiconductor region. Two exposed n-type semiconductor regions are formed on each of the p-type semiconductor regions, with a main electrode formed on the n-type semiconductor regions and the exposed p-type semiconductor region therebetween. An insulated gate extends from one of the n-type semiconductor regions in one of the p-type semiconductor regions to a closer one of the n-type semiconductor regions in an adjacent p-type semiconductor region. The length of the insulated gate is longer than a distance between adjacent insulated gates.

Vertical insulated gate semiconductor device with less influence from

In a module using a high-speed switching element such as an IGBT for a high-speed inverter, a matching condition is established between the switching characteristic of the IGBT and the recovery characteristic of the diode to be connected thereto in an anti-parallel fashion. As a result, the oscillating voltage appearing in the inverter circuit is suppressed to prevent erroneous operation of the inverter system.

Parallel circuit module including a diode and an IGBT

A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.

Method of manufacturing a power semiconductor device using implants and

Semiconductor device and manufacturing method therefor

A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.30 -source layer.

Method for fabricating insulated gate semiconductor device

A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.+ -source layer.

Disclosed is a composite semiconductor device which comprises: a second and a third semiconductor regions of a second conductivity type formed in a first semiconductor region of a first conductivity type independently of each other and so as to be exposed on one main surface of a semiconductor substrate; a fourth and a fifth semiconductor regions of the first conductivity type formed in the second semiconductor region independently of each other and so as to be exposed on the one main surface of the semiconductor substrate; a first insulated gate electrode formed on the second semiconductor region located between the fifth and first semiconductor regions and exposed on the one main surface; a second insulated gate electrode formed on the first semiconductor region located between the second and third semiconductor regions and exposed on the one main surface; an electrode which shorts the fourth and third semiconductor regions; another electrode which shorts the second and fifth semiconductor regions; and a further electrode provided in the first semiconductor region.

Composite semiconductor device

A method of fabricating a semiconductor device through selective diffusion of aluminum vapor into a silicon substrate by heating a sealed tube in which the silicon substrate and an aluminum source are disposed. The diffusion is effected with a low concentration of aluminum smaller than about 10.sup.17 atoms/cm.sup.3, thereby making it possible to use a silicon oxide film as a diffusion mask for the selective diffusion of aluminum at predetermined region of the silicon substrate.

Vapor phase diffusion of aluminum with or without boron

In a high-withstand-voltage (high-breakdown voltage) semiconductor device in which the main PN junction is of planar structure and a field limiting ring region is provided outside and around the exposed end of the main PN junction, a groove is formed between the main region to form the main PN junction and the field limiting ring region, the bottom of which groove is shallower than that of each of the regions and in the surface of which groove the end of the main PN junction and one of the ends of the PN junction between the field limiting ring region and the substrate are exposed, and the other end of the PN junction between the field limiting ring region and the substrate is exposed in the surface of another groove whose bottom is deeper than that of the field limiting ring region.

Growing community of inventors

Hitachi, Japan

Yasumichi Yasuda