Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Yasumasa Nishimura

Kazuyasu Fujishima

Masaki Kumanoya

Hideto Hidaka

Katsumi Dosaka

Hideshi Miyatake

Masaharu Moriyasu

Masanao Maruta

Keiko Ito

Hiroyuki Takeoka

The present invention comprises: a plurality of output terminals through which a signal from an internal circuit is output; buffer circuits, each provided between one of the plurality of output terminals and the internal circuit; and a delay circuit connected to the specific buffer, the delay circuit delaying the signal from the internal circuit. With this arrangement, it is possible to measure a delay time from an input test signal even when a super-high-speed device is tested.

Semiconductor device, test method for semiconductor device, and tester for semiconductor device

Testing apparatus and method of measuring operation timing of semiconductor device

Burst pressure P of an insulating layer positioned immediately on a fuse layer is defined by using planar width W of fuse layer and thickness t of insulating layer. The value of the planar width W of fuse layer and the value of the thickness t of insulating layer are set such that the value of burst pressure P is at most about 1000 kg/cm.sup.2. The value of the thickness t and the value of the planar width W are set such that the value t/W is at least 0.45 and at most 0.91. Consequently, stable fuse blowing becomes possible while reducing manufacturing cost.

Semiconductor device having a fuse layer

A DRAM has a stacked capacitor. The stacked capacitor is formed of a first portion extending on an insulating layer on the substrate, a cylindrical second portion extending vertically upward from the first portion, and a third portion extending from the second portion to have an eaves-like shape, so as to increase charge storage capacity. The structure increases opposing areas between the electrodes of the capacitor, increasing the capacitor capacity. Between the adjacent capacitors, the projecting eaves-like third portions are overlapped with each other without contact, so as to increase the area of the third portions. By this structure, the marginal space between memory cells can be utilized as capacitor region.

Stacked capacitor type dynamic random access memory

A redundancy-secured semiconductor device, comprising: primary semiconductor elements and secondary semiconductor elements, the secondary elements being spare, redundant elements for performing the functions of the primary elements that may contain faults. The primary elements are selectively disabled if a fault is found during a redundancy test and a secondary element is substituted therefor. The substituted secondary element is then tested for performance criteria at the time of the redundancy test.

Redundancy-secured semiconductor device

A semiconductor memory comprises memory cells (15-18, 27-30), a data writing terminal (1), a data readout terminal (48), transistors (3-10, 35-42), address signal input terminals (23-26), subdecode signal input terminals (43-46), driving signal generating circuits (49-52), parallel readout circuits (79-82) and test mode switching signal input terminal (53, 88). In writing of function test data for the memory cells, the driving signal generating circuits turn all of the transistors (3-10) on in response to a test mode switching signal with no regard to address signals, thereby to simultaneously write data in the memory cells (15-18). Further, in readout of the function test data for the memory cells, the parallel readout circuits read the storage contents of the memory cells (27-30) storing the test data in response to a test mode switching signal with no regard to subdecode signals. Logic circuit means (90, 91, 94) may be provided to output logical value corresponding to the test data stored in the memory cells when all of the logical values of the test data are at the same level.

Semiconductor memory

A semiconductor device is provided which can be efficiently subjected to a function test at a high speed by write/read operations for each plurality of bits. The semiconductor device according to the present invention comprises an encoder for encoding a 1-bit signal to a signal of a plurality of bits and a decoder receiving a signal of a plurality of bits for decoding the same to a 1-bit signal in response to the states thereof, so as to simultaneously write each bit of the plurality of bits from the encoder in each corresponding memory cell of a plurality of simultaneously selected memory cells in a writing test mode, and to simultaneously read information signals stored in the plurality of simultaneously selected memory cells in a reading test mode thereby to decode the signals to a 1-bit signal corresponding to the plurality of information signals.

Growing community of inventors

Tokyo, Japan

Yasumasa Nishimura