Tektronix, Inc.

Tektronix International Sales Gmbh

Yasumasa Fujisawa

Raymond L Veith

Steven K Sullivan

Iwao Akiyama

Yukio Aizawa

A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channelsandhave signal generation blocksandthat have clock phase shift circuitsand, memories, parallel to serial converters and DACs respectively. A phase comparatorcompares data reading clocks from the signal generation blocksandto produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocksand. A CPU controls the clock phase shift circuitsandaccording to the phase difference signal to shift phases of the clocks provided to the signal generation blocksandand then makes phase relationship between the output signals of the first and second channelsandas desired.

Phase controllable multichannel signal generator having interleaved digital to analog converters

A data generator provides faster data than before. A parallel data generatorprovides first data having four or five effective data width according to a divided clock DCLK. A bit width adjusterhaving a FIFO memory receives the first parallel data to provide second parallel data of constant four bit width despite of the bit width of the first parallel data. A parallel to serial converterconverts the second parallel data into serial data according to a reference clock RCLK that is faster than divided clock DCLK. The frequency of the divided clock DCLK can be constant, which makes it possible to use DLL to fasten the operation of the logic circuits.

Data generator for generating data of arbitrary length

A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channelsandhave signal generation blocksandthat have clock phase shift circuitsandmemories, parallel to serial converters and DACs respectively. A phase comparatorcompares data reading clocks from the signal generation blocksandto produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocksandA CPU controls the clock phase shift circuitsandaccording to the phase difference signal to shift phases of the clocks provided to the signal generation blocksandand then makes phase relationship between the output signals of the first and second channelsandas desired.

Phase controllable multichannel signal generator

A triggered data generator reduces timing jitter at the start of serial data output from arrival of a trigger signal. A trigger detecting circuitproduces trigger phase information indicating the phase relationship between the trigger signal and a reference clock. A data pattern generating circuitgenerates parallel data bits according to the reference clock in response to the trigger signal. A data shifting circuitrearranges the parallel data bits in a predetermined order to produce shifted parallel data bits in which data bit order is shifted relative to the reference clock as a function of the trigger phase information. A parallel to serial converterconverts the shifted parallel data bits into serial data bits.

Triggered data generator

A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.

DDS pulse generator architecture

A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.

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Kanagawa, Japan

Yasumasa Fujisawa