Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Elpida Memory, Inc.

Hitachi Engineering Co., Ltd.

Yasuko Yoshida

Shuji Ikeda

Norio Suzuki

Norio Ishitsuka

Hideo Miura

Shinichi Horibe

Masayuki Kojima

Akira Takamatsu

Kazushi Fukuda

Akio Nishida

Kozo Watanabe

Hirohiko Yamamoto

Kota Funayama

Masamichi Kobayashi

Hirofumi Shimizu

Yasushi Matsuda

Toshio Nozoe

Koichi Imato

Koichiro Ishibashi

Kenichi Osada

Kunio Uchiyama

Toshiaki Yamanaka

Yasuhisa Shimazaki

Keiichi Yoshizumi

Norio Nakagawa

Atsushi Ogishima

Keiji Okamoto

Hiroyuki Ichizoe

Maki Shimoda

Mitsuyuki Kimura

Kenji Shiozawa

Takashi Hashimoto

Satoshi Sakai

Kousuke Okuyama

Kazuhiro Komori

Tatsuyuki Saito

Hidenori Suzuki

Atsushi Hiraiwa

Takayuki Kanda

Kenji Kanamitsu

Soichiro Hashiba

Hideaki Tsugane

Michimasa Funabashi

Fumiyuki Kanai

Kazuo Yoshizaki

Hiroshi Ashihara

Katsuhiro Uchimura

Kazushi Tomita

Tsuyoshi Tabata

Ken Okutani

Kohji Yamasaki

Shuji Matsuo

Yutaka Takeshima

Chiemi Hashimoto

Motoko Kawashima

Junichi Takano

Mitsugu Oshima

Uitsu Tanaka

Noriyuki Yabuoshi

Sousuke Tsuji

Hideo Miwa

Mitsuhiro Higuchi

Kenichi Kuroda

Masataka Minami

Hideyuki Matsuoka

Shinichiro Kimura

Naotaka Hashimoto

Yutaka Hoshino

Eiichi Murakami

Shiro Kamohara

Masaru Nakamichi

Kyoichiro Asayama

Satoru Haga

Eri Okamoto

Yuuki Koide

In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

Semiconductor integrated circuit device

A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSilayer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

Manufacturing method of semiconductor device

Method of manufacturing a semiconductor integrated circuit device

A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Semiconductor device and process for producing the same

A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

Semiconductor integrated circuit device and a method of manufacturing the same

A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSilayer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.

Semiconductor integrated circuit device with a metallization structure

SRAM having an improved capacitor

A semiconductor integrated circuit device, e.g., a memory cell of an SRAM, is formed of a pair of inverters having their input and output points connected in a crisscross manner and being formed of drive n-channel MISFETs and load p-channel MISFETs. The n-channel MISFETs and p-channel MISFETs have their back gates supplied with power supply voltage and a ground voltage, respectively. The MISFETs are formed with a metal silicide layer on the gate electrodes G and source regions (hatched areas) and without the formation of a metal silicide layer on the drain regions, respectively, whereby the leakage current of the MISFETs due to a voltage difference between the drain regions and wells can be reduced, and, thus, the power consumption can be reduced.

A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

Semiconductor integrated circuit device including MISFETs each with a gate electrode extended over a boundary region between an active region and an element isolation trench

A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

Process for producing semiconductor device and semiconductor device produced thereby

A protection film is formed on a silicon oxide film formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.

Method of manufacturing a multilayer metallization structure with non-directional sputtering method

An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

Semiconductor integrated circuit and method for manufacturing the same

Growing community of inventors

Sayama, Japan

Yasuko Yoshida