Panasonic Corporation

Yasuko Tabata

Akio Misaka

Hideyuki Arai

Takayuki Yamada

Takehiro Hirai

Yuji Nonami

A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.

Semiconductor device and layout design method for the same

A semiconductor device includes a circuit portion including at least one real feature, and a plurality of dummy feature groups each including a plurality of dummy features spaced apart from each other by a first distance. The plurality of dummy feature groups are spaced apart from each other by a second distance larger than the first distance, and the circuit portion and the plurality of dummy feature groups are spaced apart from each other by the second distance.

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Shiga, Japan

Yasuko Tabata