Fujitsu Corporation

Yasuko Shirai

Hideaki Kurihara

Yoshinori Tanaka

Yoshihiro Sakai

Tomohiko Taniguchi

Yoshinori Soejima

Teruyuki Sato

Kazuhiro Nomoto

Masato Ito

A CODEC has a DSP which can consecutively execute a plurality of algorithms without restriction of a memory capacity. The DSP performs an encoding/decoding operation on a digital signal. A program memory stores a program divided into a plurality of block programs, the program being stored on an individual block program basis. A data memory stores a set of data used for executing each block program stored in the program memory, the set of data being divided into a plurality of data blocks and stored on an individual data block basis. A program executing unit executes each block program stored in the program memory by using a corresponding data block stored in the data memory. A program changing unit obtains a new block program from an external device each time execution of one of the block programs by the program executing unit is completed so as to store the obtained new block program in the program memory.

CODEC for consecutively performing a plurality of algorithms

A speech signal coding apparatus inputs a pitch period generated by coding a speech signal, and outputs information on a range for said pitch period, together with the pitch period. A speech signal decoding apparatus inputs the pitch period and the above information on the range, and determines whether or not the pitch period is within the range. When the pitch period is determined to be within the range, the speech signal decoding apparatus outputs the above pitch period. When the pitch period is determined not to be within the range, the speech signal decoding apparatus outputs as a pitch period a predetermined value within the range.

Speech signal coding and decoding system transmitting allowance range

Growing community of inventors

Kawasaki, Japan

Yasuko Shirai