Nec Corporation

Yasuko Hanagama

Toyokazu Nakamura

Kiyoshi Nikawa

Tohru Tsujide

Kenji Morohashi

In a fault analysis of large-scale integrated (LSI) circuits, a potential distribution image of a non-defective product and another potential distribution image of a defective product are displayed alternately and continuously in time, so that it is possible to acquire in real time an image of any location within a whole surface of the LSI chip. As a result, it can be viewed as if the potential distribution image of the non-defective product and the potential distribution image of the defective product are overlapped or superimposed with over time. Accordingly, a different portion between the non-defective and defective potential distribution images can be seen distinguishably from a coincident portion between the non-defective and defective potential distribution images, so that it is possible to trace the different portion in real time.

System and method for fault analysis of semiconductor integrated circuit

A semiconductor integrated circuit fault analyzing apparatus includes an electron beam tester and controller. The electron beam tester includes an electron gun assembly for generating a primary electron beam and forms a voltage contrast image on the basis of a detection amount of secondary electrons obtained by irradiating the primary electron beam from the electron gun assembly onto a semiconductor integrated circuit serving as a target to be tested and supplied with a test pattern signal, thereby specifying a faulty circuit portion of the semiconductor integrated circuit using the formed voltage contrast image. The controller sets, immediately before the test pattern signal is supplied to the semiconductor integrated circuit, at least one of a power and a signal which are supplied to the semiconductor integrated circuit to be a voltage different from a voltage obtained in the presence of the test pattern signal to cause the electron beam tester to acquire a voltage contrast image free from charge-up phenomena in synchronism with the start of supplying the test pattern signal.

Semiconductor integrated circuit fault analyzing apparatus and method

The invention provides an apparatus for diagnosing a void within a conductive material for interconnections of semiconductor integrated circuits. A laser beam irradiating section is provided for supplying a thermal wave to interconnections of the semiconductor integrated circuits to cause a rise of a temperature of the conductive material due to a thermal accumulation around a void within the conductive material, the thermal wave supplying section being able to move in a plane for accomplishment of a scanning operation of the thermal wave supply. A voltage applying section is connected to the interconnections. A current detecting section is connected to the interconnections for detecting an amount of an electrical current flowing through any part of the interconnections to sense a variation of the amount thereof on account of the rise of the temperature of the conductive material due to the thermal accumulation around the void within the conductive material so as to detect any void within the conductive material.

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Tokyo, Japan

Yasuko Hanagama