Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Yasuki Tanabe

Takashi Miyamori

Katsuyuki Kimura

Keiri Nakanishi

Masato Sumiyoshi

Ryuji Hada

Shunichi Ishiwata

Takahisa Wada

Wataru Asano

Toru Sano

Yasukazu Okamoto

Kazuki Inoue

Hui Xu

Tsuyoshi Nakano

An operation device according to an embodiment includes an operation instruction circuit, an operation circuit, a buffer and a storage area instruction circuit. The operation instruction circuit issues an operation instruction for an operation type of either one of a first operation and a second operation. The operation circuit performs an operation in accordance with the operation instruction, and outputs an intermediate operation result. The buffer stores the intermediate operation result. The storage area instruction circuit specifies an area within the buffer in Which the intermediate operation result is stored, according to the operation type.

Operation device and operation system

A data compressing device according to an embodiment includes a data cutting unit configured to divide continuously inputted data into W-bit data blocks and to output the data blocks in segments such that each of the segments is composed of N data blocks, and a compression-method determining unit configured to select, as a compression portion for each of the segments, a run length system, a flag system, or no compression, according to a ratio of data blocks of specific data in any of the segments. The data compressing device further includes an RL compression unit configured to execute, on any of the segments, a run length system of storing a consecutive amount of the specific data into compressed data, and a flag compression unit configured to execute, on any of the segments, a flag system of storing positional information of the specific data into compressed data.

Data compressing device, data decompressing device, and data compressing/decompressing apparatus

According to one embodiment, an image processing apparatus connectable to a main memory in which a plurality of pixel values of unconverted image is stored and a cache memory including a plurality of cache blocks. The apparatus includes a counter, a coordinate determination module, a memory controller, a cache access module, a pixel value calculator, and an output module. The counter determines a coordinate within converted image according to a predetermined execution sequence. The coordinate determination module determines a plurality of coordinates within unconverted image of the pixel values of unconverted image necessary to calculate a pixel value of converted image corresponding to the coordinate within converted image. The memory controller transfers the pixel values of unconverted image stored in the main memory to the cache blocks corresponding to each of the coordinates within unconverted image. The cache access module reads out all the pixel values of unconverted image necessary to calculate the pixel value of converted image from the cache blocks. The pixel value calculator calculates the pixel value of converted image by referring to the pixel values of unconverted image read out by the cache access module. The output module outputs the pixel value of converted image.

Image processing apparatus, image processing system, and method for having computer process image

An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Image processor and command processing method

According to one embodiment, an image processing apparatus connected to an external memory and a cache memory. The apparatus includes a counter, a coordinate calculator, a tag checker, a pixel referring module, a pixel value calculator and an outputting module. The counter determines a converted coordinate according to a predetermined execution sequence. The coordinate calculator calculates a unconverted coordinate used to calculate a converted pixel value located at the converted coordinate. The tag checker generates a conversion request to calculate the converted pixel value with reference to an unconverted pixel located at the unconverted coordinate. The pixel referring module reads the unconverted pixel from the cache memory based on the conversion request when the unconverted pixel is stored in the cache memory. The pixel value calculator calculates the converted pixel value with reference to the read unconverted pixel. The outputting module writes the converted pixel having the calculated converted pixel value into the external memory.

Image processing apparatus and image processing system

According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Compiling device and compiling method

An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Growing community of inventors

Tokyo, Japan

Yasuki Tanabe