Fujitsu Corporation

Fujitsu Semiconductor Limited

Socionext Inc.

Yasuki Nakamura

Hideo Miyake

Atsuhiro Suga

Ryo Kuya

Tatsuya Yoshino

Hiroshi Terashima

Masaharu Kimura

Takahisa Suzuki

Satoshi Imai

Makiko Ito

Yoshio Hirose

Yoshimasa Takebe

Hiroshi Okano

Teruhiko Kamigata

Hitoshi Yoda

Michihide Kimura

A simulation apparatus is disclosed, including a group switching part. The group switching part refers to a priority management table, which manages priority information of priorities to assign a CPU for multiple groups of tasks stored in a storage area, and changes the priorities of the multiple groups of tasks, when an event occurs to activate a task to be executed in verifying of software by using a simulation.

Simulation apparatus, method, and computer-readable recording medium

A simulation apparatus is disclosed, including a hardware simulator and a CPU model. The hardware simulator activates one or more logical hardware models for verifying embedded software. The CPU model is one of the one or more logical hardware models which imitates a CPU which executes the embedded software, and to trigger the embedded software to operate without synchronization for each of instructions.

Simulation apparatus, computer-readable recording medium, and method

A simulation program stored in a computer readable recording medium to execute a simulation of first and second simulation objects is provided. The simulation program includes a storage that stores one of an initial state, a read waiting state and a write waiting state for a channel used for data transfer between the first and second simulation objects; a receiver that receives a read request from the first simulation object to the second simulation object through the channel; a judgment unit which, upon reception of the read request, judges whether a state corresponding to the channel is the read waiting state; a transmitter which transmits data corresponding to the channel stored in a storage area to the first simulation object when judging to be the read waiting state; and a changer that changes the state to the initial state based on the data transmission.

Simulation program and simulation apparatus

A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information.

Multiprocessor system and control method thereof

When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (), a normal previous state register (), and a normal factor register (). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (). By referring to the flag register () in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.

Interrupt control apparatus and method

A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.

Parallel Processor efficiently executing variable instruction word

In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.

Information processing unit, and exception processing method for specific application-purpose operation instruction

The present invention relates to a processor that performs a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations. The present invention also relates to a method of controlling such a processor. This processor includes a history control unit that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address.

Processor and method of controlling the same

In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.

Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory

The present invention provides a processor system having a main processor that efficiently executes coprocessor instructions, regardless of the type of each coprocessor to which the main processor is connected. When a coprocessor instruction to instruct execution by a coprocessor is supplied, the main processor determines whether or not the supplied coprocessor instruction has a possibility of having control dependency on a preceding coprocessor instruction being executed by a corresponding one of the coprocessor, in accordance with an instruction field corresponding to the supplied coprocessor instruction. If the supplied coprocessor instruction has the possibility of having the control dependency, the main processor issues the supplied coprocessor to the corresponding one of the processors only after the execution of the preceding coprocessor instruction is completed.

Processor and processor system

When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register ( ), a normal previous state register ( ), and a normal factor register ( ). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register ( ). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register ( ). By referring to the flag register ( ) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.

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Kawasaki, Japan

Yasuki Nakamura