Kabushiki Kaisha Toshiba

Canon Kabushiki Kaisha

Toshiba Electronic Devices & Storage Corporation

Yasukazu Noine

Kenji Matsuo

Kazuhiko Kasai

Masaji Ueno

Kenji Shino

Shinji Fujii

Yasuhisa Shintoku

Atsushi Hosokawa

Nobuyuki Shobudani

Yoshihiro Kato

Yoshiharu Katayama

Kazuaki Umetsu

According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.

Semiconductor device

A semiconductor circuit according to the present embodiment comprises a driving circuit, a determining circuit, and a control circuit. The driving circuit includes a first switching element, a second switching element, a third switching element, and a fourth switching element. The comparing circuit compares a potential of the one terminal of the load or a potential of the other terminal of the load. The determining circuit determines, based on output of the comparing circuit, either one or both of a state of the load and a state of the driving circuit. The control circuit controls the driving circuit.

Semiconductor circuit and failure determination method for semiconductor circuit

A driving circuit includes a plurality of output terminals to be electrically connected to scan wirings, respectively, a scan controlling unit for selecting one or plural output terminals to output a driving signal for the scan wiring from among the plurality of output terminals, and a potential correcting unit for controlling a potential of the driving signal on the basis of a difference voltage between the potential of the selected output terminal and a reference potential. In addition, a reference potential adjusting unit adjusts the reference potential in response to a current passing through the selected output terminal in order to correct a voltage drop caused by a member connected to the selected output terminal. The reference potential adjusting unit changes adjustment of the reference potential in response to the number of the selected output terminals and turns off adjustment of the reference potential in the case that the number of the selected output terminals is more than 1.

Driving circuit and image display apparatus

A drive circuit of a display panel having wirings and display devices connected to the wirings includes a first switch that transits potential of the wirings toward a first potential, a feedback amplifier that maintains the potentials of the wirings at the first potential, and a second switch that selects whether or not to supply an output from the feedback amplifier to the wirings. In addition, a self switch controls the second switch by comparing the potential of the wirings with a reference potential that is higher by a predetermined value than the first potential. The first switch and the second switch are connected to the wirings in parallel, and a drive performance of the first switch is lower than that of the second switch.

Drive circuit of display panel and display apparatus

A drive circuit includes a drive transistor connected at a pair of its main electrodes respectively to a drive output terminal side and a reference voltage source VEE side, an operational amplifier for controlling an output voltage that is output from the drive transistor, a detection transistor for detecting a current that flows through the drive transistor, a first feedback loop for detecting an output voltage at the drive output terminal and feeding back the output voltage to the operational amplifier, and a second feedback loop for detecting an output current of the detection transistor and feeding back the output current to the operational amplifier. The drive transistor and the detection transistor form a mirror circuit.

Drive circuit

A CMOS level converter including two CMOS inverter that are complimentary coupled with each other. Each of the CMOS inverter includes two MOS transistors and is coupled between a source voltage and a ground potential in series. When an input signal begins to change from a low level to a high level, one of the MOS transistors in an input side CMOS inverter is turned off, and the inverter is coupled through a diode to the ground potential. As the input level rises gradually, on the input side inverter, due to a high level output from an output side inverter, the MOS transistor turns on. As a consequent, the output is set at the ground potential in the level conversion, even when the amplitude is insufficient.

Level converter

A low-voltage output circuit has the first and the second MOS transistors. An input signal is fed to the gate of the first transistor. Either of the source and the drain of the first transistor is supplied with a predetermined potential. The other is connected to an output terminal and generates an output signal. The first transistor raises the output signal to the predetermined potential level in response to the input signal. Either of the source and the drain of the second MOS transistor is connected to the gate of the first transistor. The other is connected to the output terminal. The circuit further includes a device for supplying a bias voltage to a gate of the second transistor so that the first and second transistors remain turned off at different gate bias potentials and the second transistor turns on before the first transistor when the output signal is raised to the predetermined potential level to keep the first transistor remaining turned off. The circuit further includes a device for restricting current flow from the output terminal to the predetermined potential side through the first and second transistors.

Low-voltage output circuit for semiconductor device

An output circuit has a bipolar transistor circuit of a 1st and a 2nd bipolar transistor connected in Darlington configuration. The base of the 1st transistor is supplied with an input signal. The collector of the 2nd transistor is connected to a power supply through a 1st diode. And, a signal is outputted from the emitter of the 2nd transistor. The output circuit also includes a 1st PMOS transistor. The source of the 1st PMOS transistor is connected to the base of the 2nd transistor, its drain being grounded, and its the backgate being connected to the power supply through the 1st diode. The output circuit may further includes a 2nd PMOS transistor having a source and a backgate both connected to the power supply, a drain connected to the base of the 2nd transistor through a second diode, and a gate supplied with an inverting signal of the input signal. The output circuit may further includes: a 2nd PMOS transistor connected between the drain of the 1st PMOS transistor and ground, having a source and a backgate both being grounded, a drain connected to the drain of the 1st PMOS transistor, and a gate supplied with the input signal; and a 3rd bipolar transistor having a base connected to the drain of the 1st PMOS transistor, a collector connected to the base of the 2nd transistor, and an emitter being grounded.

Output circuit in Darlington configuration

In an output circuit, a signal /.phi. opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal .phi. in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /.phi. changes at an output terminal 4) to another delay time (to when the level of the signal .phi. changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/.phi. and .phi. at two output terminals 4 and 5.

In-phase signal output circuit, opposite-phase signal output circuit,

A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.

Differential current source circuit in DAC of current driving type

In a sense amplifier circuit, an output potential is set in a data output state when an operation of the sense amplifier is a worst pass before the start of read access. In a memory read mode, when data corresponding to the worst-pass operation of the sense amplifier circuit is read out, the circuit is previously set in a corresponding data output state. A time delay (gate delay) by a gate does not occur. In contrast, when data corresponding to the best-pass operation of the sense amplifier circuit is read out, the gate delay occurs by this operation. The gate delay, however, is shorter than that of the worst pass. As a result, only the best pass is present as the operation mode of the sense amplifier circuit. Therefore, a high operation speed is achieved, so that a high read speed of the entire memory is achieved.

Sense amplifier circuit

This invention discloses a switching constant current source circuit including a first current path for supplying a constant current, a first MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a second current path, and a gate of which is applied with a digital signal corresponding to a logical amplitude, a second MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a third current path, and which performs a switching operation complementary with the first MOS transistor, and level conversion means for fetching a change in voltage in the first current path caused by a change in current flowing through the first current path according to an operation of the first MOS transistor in response to the digital signal, and alternately applying a first level for disabling the second MOS transistor, which operates complementarily with the first MOS transistor, and a second level for enabling the second MOS transistor to output a predetermined current.

Switching constant current source circuit

A MOS transistor includes a gate electrode layer formed on an insulation layer which is formed on an element formation region defined by a field insulation layer formed on a P-type semiconductor substrate. The gate electrode layer has first and second openings formed therein. Further, N-type impurity diffusion regions acting as the drain and source of the MOS transistor are formed in those portions of the surface area of the semiconductor substrate which lie under the first and second openings.

MOS transistor and differential amplifier circuit with low offset

This invention is a D/A converter including a preset current source, first and second differential switches for selectively deriving an output current of the preset current source in response to complementary signals supplied to control electrodes thereof, and an imaginary short circuit for connecting output portions of current paths of the switches to each other. Variation in the voltage at the time of switching operation of the differential switch can be suppressed by use of the imaginary short circuit with the above construction, thus making it possible to enhance the operation speed.

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Chigasaki, Japan

Yasukazu Noine