Nec Corporation

Elpida Memory, Inc.

Other

Yasuji Koshikawa

Chiaki Dono

Tadahiko Sugibayashi

Takahiro Hara

Yasuhiro Matsumoto

Kouji Mine

Jun Suzuki

Sumio Ogawa

Tomoko Nobutoki

Hiromasa Noda

Masayuki M Nakamura

Yoshiro Riho

Yasuhiro Takai

Shuichi Kubouchi

Ryuji Yamamura

Hisashi Abo

Yousuke Kawamata

Junya Taniguchi

A semiconductor device includes a memory cell, a bit line coupled to the memory cell, first and second wells arranged adjacently to each other, the first and second wells being different in conductivity type from each other and defining a boundary therebetween, first and second transistors formed in the first and second wells, respectively, and being different in channel type from each other, gate electrodes of the first and second transistors being connected in common to the bit line, and a third transistor formed in the first well such that the third transistor is sandwiched between the boundary and the first transistor, and a gate of the third transistor being supplied with a bit line precharge signal.

Semiconductor device

A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and are disposed in the center region of the well, while non-sensitive element is disposed in the peripheral region close to the boundary in the well. Since sensitive element requiring precise control of threshold voltage is disposed in the center region having uniform impurity density, and non-sensitive element allowing for less precise control of threshold voltage is disposed in the peripheral region suffering from uneven impurity density, it is possible to effectively use the overall area of the well and to thereby suppress an increase in the layout area of chips.

Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant address is recorded and a redundancy selection signal is output when an access address is coincident with the programmed address. It is presupposed that repair addresses are programmed from the first to the n-th redundancy ROM circuits in an ascending order with regards to address. If it is detected under this condition that a redundancy selection signal has been output from the i+1'st redundancy memory circuit while no redundancy selection signal is being output from the i-th redundancy memory circuit, an SR flip-flop is set and the sequence of the substitution decision outputs is decided to be a reversed sequence.

Redundancy circuit and semiconductor memory device

There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.

Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address

A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array, a row decoder, and a sense amplifier, surrounded by a bold broken line. Thick-film transistors having a threshold voltage lower than the aforementioned transistors are used for input bufferstoand an input/output buffer, surrounded by a bold line. Thin-film transistors are used for a clock generator, a command decoder, a mode register, a controller, a row address buffer and refresh counter, a column address buffer and burst counter, a data control circuit, a latch circuit, a DLL, and a column decoder

Semiconductor memory device

A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuitsis configured to store a first data defining the circuit configuration. A fuse element circuitis configured to store a second data representing inhibition of programming the group of fuse element circuits. A control logic circuitis configured to program the first and the second data on the fuse element circuits. An AND gate circuitis configured to inhibit the control logic circuitfrom programming the group of fuse element circuitson condition that the fuse element circuithas been programmed.

A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.

Semiconductor memory device having a refresh cycle changing circuit

Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh.

A semiconductor memory device includes first and second bus regions, a third bus region laid out along a center line, a first cell region laid out between a first side and the first bus region, a second cell region laid out between a second side and the second bus region, third and fourth cell regions laid out between the first and second bus regions and laid out toward a third side and a fourth side respectively seen from the third bus region, and a data input/output pad string laid out along the third bus region.

Semiconductor memory device having plural memory cell arrays

In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.

A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.

Semiconductor memory device which controls refresh of a memory array in normal operation

Semiconductor storage device

In a semiconductor device, an internally-generated power supply voltage VPP is monitored. If the internally-generated power supply voltage VPP is lower than a lower limit voltage, serial refresh is selected as a double refresh operation mode. In the serial refresh, double refresh for a pair address is inserted in a next refresh cycle. By the serial refresh, decrease of the internally-generated power supply voltage VPP is suppressed.

A semiconductor memory device includes a refresh counter that outputs an address of a word line to be refreshed, a ROM circuit that stores a relevant address related to a refresh defective address, and a multiple refresh control circuit that simultaneously or continuously activates the refresh defective address and the relevant address within one refresh cycle in response to a fact that the ROM circuit detects the relevant address. The multiple refresh control circuit excludes a pattern having a risk that a power supply potential or a ground potential varies greatly such as a pattern that the multiple refresh occurs continuously. With this arrangement, a refresh defective cell can be saved while restricting the variation in the power supply potential or the ground potential.

Growing community of inventors

Tokyo, Japan

Yasuji Koshikawa