Texas Instruments Corporation

Hitachi, Ltd.

Yasuhito Ichimura

Shunichi Sukegawa

Kazuya Ito

Takumi Nasu

Shoji Wada

Makoto Saeki

David R Brown

Ken Saitoh

Kohsuke Ikeda

Hiroshi Ikeda

Satoshi Nakayama

Yoritaka Saito

Yoojoon Moon

Yoshinobu Matsumoto

The objective of this invention is to reduce the layout area while guaranteeing data retention stability in a static type semiconductor memory cell. This SRAM cell is constituted with two MOS transistors and and one inverter circuit . The source terminal of PMOS transistor is connected to bit line (BL), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to word line (WL). The source tenninal of NMOS transistor is connected to a supply voltage terminal that provides low-level reference potential V (for example, zero volts), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to the output terminal o inverter circuit . The input terminal of inverter circuit is connected to data storage node (Na).

Semiconductor memory cell and semiconductor memory device

An address decoder with low power consumption of feedthrough current, leakage current, etc. Address bits AY0.sub.0 -AY0.sub.7 are respectively supplied to n-type gate terminals of CMOS transfer gates C.sub.0 -C.sub.7 and the gate terminals of PMOS transistors P.sub.0 -P.sub.7. Inverted address bits AY0.sub.0- -AY0.sub.7- are supplied to p-type gate terminals of the CMOS transfer gates C.sub.0 -C.sub.7. Enable signals AY3.sub.p, AY6.sub.q are respectively input to both input terminals of a NAND circuit 10. The output terminals of NAND circuit 10 are connected to the input terminals of CMOS transfer gates C.sub.0 -C.sub.7. The output terminals of CMOS transfer gates C.sub.0 -C.sub.7 are connected to the input terminals of the drivers D.sub.0 -D.sub.7 and the drain terminals of the PMOS transistors P.sub.0 -P.sub.7 via a node F.sub.0 -F.sub.7. The source terminals of PMOS transistors P.sub.0 -P.sub.7 are connected to a power supply voltage V.sub.cc, for example of 3.3 V. The output terminals of drivers D.sub.0 -D.sub.7 are connected to Y-address lines YS.sub.0 -YS.sub.7.

Address decoder

A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry. In response to the second signal, the row control and column control circuitry makes the banks of the array selectable in a second plurality. For example, the array may originally be arranged in four banks, but by the placing the proper signal at the input of the bond option circuit, the array is selectable as a two-bank array.

Memory configuration circuit and method

Electric charge transmit elements (QD) transmit electric charge from a terminal side (NA) to a control electrode side (NB) of the circuit. The voltage at the control electrode side (NB) is raised by a capacitor configuration (CB). Voltage stabilizing elements (QC) are connected in parallel to the electric charge transmit elements between the terminal side and the control electrode side. In transferring the electric charge from the control electrode side (NB) to the other terminal side (NC), the voltage at the control electrode side (NB) is kept higher than the other terminal side (NC). Therefore, because loss of voltage by the electric charge transfer elements (QB) in transferring the electric charge is eliminated, a predetermined voltage is obtained efficiently in a short time, and a highly reliable booster circuit is provided.

Plural stage voltage booster circuit with efficient electric charge

Growing community of inventors

Kasama, Japan

Yasuhito Ichimura