Opnext Japan, Inc.

Oclaro Japan, Inc.

Yasuhisa Semba

Susumu Sorimachi

Yutaka Inoue

Hiroshi Moriya

Yoshihiko Iga

Kouichi Kouzu

By forming upper-bank patterns made of Au with a thickness of 1.5 &#x3bc;m or larger on bank portions, a solder material on a submount and a surface of a conductive layer in an upper part of a ridge portion of a laser chip are separated so as not to be in contact with each other, thereby preventing the stress generated in a bonding portion when bonding the laser chip and the submount from being applied to the ridge portion.

Semiconductor optical device

In a multi-beam semiconductor laser device, relative difference in shear strain applied to each of light-emitting portions of a laser chip mounted on a submount is suppressed, thereby reducing relative difference in polarization angle. A semiconductor laser element array mounted on a submount has a structure in which a semiconductor layer having two ridge portions is stacked on a substrate, and Au plating layers are formed on the surfaces of p type electrodes formed on the ridge portions. In each of the ridge portions, a central position of the Au plating layer in a width direction is intentionally displaced with respect to a central position of the underlying light-emitting portion in a width direction, so that shear strain is applied to each of the light-emitting portions at a stage before the semiconductor laser element array is mounted on the submount.

Semiconductor laser device

A multibeam semiconductor laser diode having: an n-type semiconductor substrate; an n-type clad layer, an active layer, a p-type clad layer and a contact layer; a plurality of partitioning grooves extending from one end to the other end of the substrate and formed from the contact layer to a predetermined depth of the p-type clad layer; a stripe-shaped ridge sandwiched between two separation grooves; an insulating layer covering an area from each side wall of the contact layer of each ridge to an end of the partitioning region via the separation groove; a first electrode formed on a second plane of the substrate; and a second electrode formed in each partitioning region covering an area above the ridge, separation grooves and multilayer semiconductor layers outside the separation grooves, the second electrode being constituted of a lower second electrode layer and an upper second plated layer.

Growing community of inventors

Saku, Japan

Yasuhisa Semba