Nippon Telegraph and Telephone Corporation

Yasuhisa Nakamura

Satoru Aikawa

Yoichi Saito

Hitoshi Takanashi

In Trellis coded modulation system in which an input digital signal in parallel form is encoded by a convolutional encoder which adds an additional bit to the input digital signal for error correction purpose, and a mapping circuit designated amplitude and phase for each symbol for QAM signal, the number of parallel bits at output of said convolutional encoder is the same as the number of parallel bits of an input digital signal. An input digital signal is first rate converted so that m+n bits in every T period is converted to m bits in every T' period, where T'=(m/(m+n)).T. The convolutional encoder adds n number of bits so that the total number of parallel bits is m+n, which is applied to the mapping circuit. In a receive side, a received signal having m+n bits in every T' period is decoded through an error correction decoder which provides m bits in every T' period, then, the decoded signal is rate converted to m+n bits in every T period. So, the number of parallel bits does not increase in spite of convolutional encoding, but a transmission rate is a little increased. The coding gain in the present invention is improved since the number of levels of the QAM signal is not increased although the bandwidth of the signal is a little increased because of the higher clock rate.

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Kanagawa, Japan

Yasuhisa Nakamura