Fujitsu Semiconductor Limited

Yasuhiro Yamazaki

Mitsuaki Hino

Instruction cache memory having a plurality of memory (for example, cache WAY), meansfor storing prediction data of a conditional branch of a branch instruction being taken or not taken and for storing prediction data of memory storing the branch instruction data of the plurality of memory when the prediction is the branch being taken, and means for, when an instruction to be executed is a branch instruction, outputting a read active control signal to the plurality of memoriesby using two pieces of prediction data obtained from the means by an index corresponding to the branch instruction, are comprised.

Data processor and memory read active control method

The present invention provides an information processing apparatus having a predecoder decoding an operation code in an input instruction, generating conditional branch instruction information indicating that the input instruction is a conditional branch instruction and instruction type information indicating a type of the conditional branch instruction when the input instruction is a conditional branch instruction, and writing the input instruction, from which the operation code is deleted, the conditional branch instruction information and the instruction type information to the instruction cache memory, and a history information writing unit writing history information indicating whether or not the conditional branch instruction was branched, as a result of executing the conditional branch instruction stored in the instruction cache memory, to an area in the instruction cache memory, where the operation code of the conditional branch instruction is deleted.

Growing community of inventors

Kahoku, Japan

Yasuhiro Yamazaki