Fujitsu Corporation

Fujitsu Microelectronics Limited

Yasuhiro Yamazaki

Hitoshi Yoda

Hiroyuki Utsumi

Atsuhiro Suga

Taizo Sato

Hiroshi Okano

Yoshimasa Takebe

Masayuki Tsuji

Teruhiko Kamigata

Taizoh Satoh

Shin-ichiro Tago

The scene change determination device of the present invention comprises a first extraction unit for extracting a plurality of pixels used for determination from the first image data, a second extraction unit for extracting pixels corresponding to the pixels extracted from the first image data, an accumulation unit for accumulating differences in value between the corresponding pixels extracted by the first and second extraction units and a determination unit for determining whether an accumulated value per image data exceeds a threshold value. The first and second extraction units slides and extracts the plurality of pixels used for determination for each field.

Scene change determination device/method and data transfer device/method

In an image processing device, a scene-change detection unit captures first data of first pixels constituting a first picture and second data of second pixels constituting a second picture with the first and second pixels thinned out, and detects a scene change in the first picture based on differences between the first and second data, where the second picture immediately precedes the first picture. A transfer control unit controls operations of reading out at intervals from a storage device data of groups of a predetermined number of pixels consecutively arranged along a horizontal direction in at least the second picture, and transferring the data of the groups to the scene-change detection unit through a data bus, where the predetermined number corresponds to the maximum number of pixels which can be concurrently transferred through the data bus, or an integer multiple of the maximum number.

Device and method for image processing

An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

Processing device for buffering sequential and target sequences and target address information for multiple branch instructions

A microprocessor includes a register and a comparator. The register stores an address area, the address area requiring a guarantee of an access order. The comparator compares an address of the address area held in said register with an address of an address area indicated in an access request from CPU, and outputs a signal to execute an access request succeeding the access request from the CPU after executing an access request preceding the access request from the CPU when the address area indicated in the access request from the CPU matches the address area held in said register.

Microprocessor executing a program to guarantee an access order

The present invention provides a data processor including an instruction cache that can operate at low power consumption, avoiding useless power consumption. The data processor includes a plurality of cache memory units, wherein only a cache memory unit that stores a demanded instruction is enabled, while other memory units are disabled.

Growing community of inventors

Kawasaki, Japan

Yasuhiro Yamazaki