Hitachi, Ltd.

Renesas Technology Corp.

Yasuhiro Uemura

Masakazu Sakaue

Akira Yamagiwa

Ryoichi Kurihara

Takashi Maruyama

Mikihiro Tanaka

Hiroshi Ito

Makoto Funatsu

Takashi Nakamura

Akio Katsushima

Nobuaki Ejima

In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.

Clock generating method and clock generating circuit

Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis. Also disclosed here is an upgraded module structure permitting a multiple-stage module setup together with an advanced cooling structure for modules.

Logic emulation module and logic emulation board

The present invention provides an information processing apparatus that may be designed in small and thin size and a small and thin CPU module that has a high heat releasing effect and is suitable therefor. The CPU module includes a processor, a connector to be electrically connected to the outside, a system control circuit for controlling transfer of a signal between the processor and the connector, and a printed board on which the processor, the connector and the system control circuit are mounted. The CPU module further provides a heat release plate one side of which is pasted with the printed board and the other side of which is substantially planar. The printed board has a cavity formed therein so that the processor may be fitted in the cavity in a bare-chip state. One side of the bare chip is jointed with the heat release plate.

Circuit module and information processing apparatus

The present invention provides an information processing apparatus that may be designed in small and thin size and a small and thin CPU module that has a nigh heat releasing effect and is suitable therefor. The CPU module includes a processor, a connector to be electrically connected to the outside, a system control circuit for controlling transfer of a signal between the processor and the connector, and a printed board on which the processor, the connector and the system control circuit are mounted. The CPU module further provides a heat release plate one side of which is pasted with the printed board and the other side of which is substantially planar. The printed board has a cavity formed therein so that the processor may be fitted in the cavity in a bare-chip state. One side of the bare chip is jointed with the heat release plate.

A packaging method of an electronic component for packaging the electronic component to a packaging substrate comprises the steps of: forming a predetermined quantity of solder bumps at connection portions of the electronic component; forming through-holes and pads on the packaging substrate in such a manner as to correspond to the solder bumps; applying a solder paste to pad portions of the through-holes and the pads formed on the surface of the packaging substrate in such a manner as to attain a specific quantity of solder components with the predetermined quantity of the solder bump; and heating the electronic component and the packaging substrate to a predetermined temperature such that button-shaped connection bumps having a predetermined height are formed between the pads and the packaging substrate so as to connect the electronic component and the packaging substrate and to keep a predetermined gap between the electronic component and the packaging substrate, and cylindrical-post connection bumps are formed between the through-holes and the packaging substrate in accordance with this predetermined gap so as to connect the electronic component and the packaging substrate. In this way, the cylindrical-post connection bumps are formed in association with the button-shaped connection bumps.

Growing community of inventors

Sagamihara, Japan

Yasuhiro Uemura