Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Tower Semiconductor Ltd.

Yasuhiro Tomita

Hitoshi Suwa

Manabu Komiya

Toshiki Mori

Seiji Yamahira

Takayuki Tanaka

Keisuke Sakai

Ryuichi Yamaguchi

Makoto Matsumoto

Seiji Yamaguchi

Noam Eshel

Kazuyuki Kouno

Nobufusa Iwanishi

Hirokazu Yonezawa

Takafumi Maruyama

Toshiyuki Shono

Akifumi Kawahara

Jeffrey Allan Jacob

Yoshiyuki Takagi

Hisakazu Edamatsu

Shigenobu Akiyama

Avi Parvin

Tamas Toth

Kenichi Yamazaki

Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories.

Voltage control circuit for providing two voltages generated based on a parameter corresponding to an input signal

Process execution control based on the internal states of flash memories and power supply circuit information

A read circuit includes a current load circuit configured to supply a load current from a power source to a first input and a second input; a first discharge circuit configured to discharge potential of the first and second inputs to a ground level; an equalization circuit configured to equalize the potential of the first and second inputs; a differential circuit configured to receive the first and second inputs as differential inputs, and to output a first output and a second read output as differential outputs; and a second discharge circuit configured to discharge potential of the first and second read outputs to the ground level.

Read circuit and non-volatile memory using the read circuit

Each of a plurality of pump stages has an input node and an output node and performs a charge pump operation in response to any one of the first and second clock signals. The plurality of pump stages include a first pump stage, in which a charge transfer transistor is connected between the input node and the output node. One end of a pump capacitor is connected to the output node, and the other end is supplied with one of the first and second clock signals corresponding to the first pump stage. A connection switcher connects to the gate of the charge transfer transistor any one of the output node of a pump stage which is supplied with one of the clock signals corresponding to the first pump stage and the input node of a pump stage which is supplied with the other clock signal not corresponding to the first pump stage and which is included in a pump stage row not including the first pump stage.

Charge pump circuit

A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor.

Semiconductor leakage current detector and leakage current measurement method, semiconductor leakage current detector with voltage trimming function and reference voltage trimming method, and semiconductor integrated circuit thereof

A nonvolatile semiconductor memory of virtual ground array in which a common connection of the sources and a common connection of the drains of nonvolatile memory cells arranged in rows and columns in a memory cell array are used as bit lines, the nonvolatile memory cells including: a reference cell from which a characteristic used as a reference in a differential readout determination operation is obtained; and a neighbor cell at one side of the reference cell, the neighbor cell sharing one of the source and the drain of the reference cell and being connected to a word line which is connected to the reference cell, wherein the nonvolatile semiconductor memory includes a neighbor cell programming circuit to set the neighbor cell to a programmed state when the word line is activated to set the reference cell to a conduction state, the neighbor cell being kept in a non-conduction state during the programmed state.

Nonvolatile semiconductor memory with virtual ground array

In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuitwrites a fail value to a neighbor cell bufferwhen all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer. The control circuitverifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.

Flash memory and program verify method for flash memory

The non-volatile semiconductor storage deviceincludes the specific command Enable/Disable signal linesconnected to the command decoder. The specific command Enable/Disable signals are externally inputted to the command decoderthrough the signal lines. Thereby, when the deviceis initialized, the command decoderenables the specific command and the devicecan shift to a mode corresponding to the specific command. On the other hand, the command decoder 108 can disable the specific command, for example, when a user uses the device, thereby preventing the specific command from being executed even when the specific command is erroneously issued.

Non-volatile semiconductor storage device with specific command enable/disable control signal

To increase a cell current ratio of a program state to an erase state of two bit storage nonvolatile memory cells and reduce power consumption, a program state of MONOS-typed memory cells is a state where electrons are injected into two local regions near drain and source junction edges, an erase state is a state where the electrons injected into the two local regions are neutralized or holes are injected, and a read bias is a linear region. A cell current in the program state can be suppressed since charges injected into the source side suppress introduction of electron carriers required for formation of a conductive channel and charges injected into the drain side limit the formation of the conductive channel near the drain side. Accordingly, a read current can be reduced, a cell current ratio can be enhanced, and moreover, a margin of a reading operation can be increased.

Driving method of nonvolatile memory and nonvolatile memory used in the same method

An n-bit status signal indicating an execution state of a write command is outputted from a status register. At the time of data writing, an output switching circuit outputs (n&#xd7;m)-bit data in which a status signal pattern repeats m times. At the time of data reading, the output switching circuit outputs data stored in a memory cell array.

Nonvolatile semiconductor memory device for outputting a status signal having an output data width wider than an input data width

Each inverter includes any of a P-channel modulation MOS transistor, a normal N-channel MOS transistor, a normal P-channel MOS transistor, and an N-channel modulation MOS transistor. A modulation substrate bias Vb of the P-channel modulation MOS transistor varies with a prescribed amplitude within the range of Vb.Vdd&minus;Vf. A modulation substrate bias Vb&prime; of the N-channel modulation MOS transistor varies with a prescribed amplitude within the range of Vb&prime;.Vss&plus;Vf&prime;. With a threshold value of the modulation MOS transistor being varied, the transition timing and waveform of a signal are varied, whereby the peak of the EMI radiation becomes gentler. As a result, EMI radiation is reduced while preventing malfunction such as latch-up.

Semiconductor integrated circuit device and electronic equipment

A probe card provides electrical connection between an IC device under test (DUT) and a testing apparatus. The probe card includes: a test chip for transferring a signal between the DUT and the testing apparatus; and a contact bump provided at a position corresponding to a pad of the test chip, wherein the test chip is provided to securely press the contact bump against the DUT, thereby establishing the electrical connection between the DUT and the contact bump.

Probe card

A semiconductor chip having an internal circuit providing a prescribed function is provided. The semiconductor chip includes: a signal pad to be used for input and/or output of a signal to and/or from the internal circuit; a first power supply pad to be used for supplying electric power to the internal circuit both in a mounted condition and in an operational test with a probe; and a second power supply pad to be used for supplying electric power to the internal circuit in the operational test with the probe.

Semiconductor chip and semiconductor wafer having power supply pads for

A signal propagation time in an integrated circuit can be calculated based on a signal delay time in each of the cells composing the integrated circuit. The signal delay time in each cell can be calculated from the load capacity of a wire connected to an output terminal of the cell and from the slew of the waveform of an input signal. To calculate the slew of the waveform of the input signal, it is required to trace back the path of the input signal. When a feedback loop exists in the integrated circuit, the process of tracing back the path of the input signal may result in an endless loop. To prevent the occurrence of the endless loop, if an input terminal for a clock signal is present in a cell having an output terminal at which a signal waveform is not calculated, the signal waveform at the output terminal is calculated based on the waveform of the clock signal. In addition, a directory in which the correspondence of the output terminal and the input terminal is recorded is produced so that the signal waveform at the output terminal can be calculated based on the signal waveform at the corresponding input terminal recorded in the directory.

Method and apparatus for calculating slew rates and signal propagation

Signal propagation delay in an inverter chain having a first inverter cell and a second inverter cell connected by an intercell wire, is evaluated. In order to guarantee that a first inverter cell delay is always evaluated to be positive (A) a logic threshold voltage for an increase in input pin voltage of the first inverter cell is set to a voltage below a switching threshold voltage of the first inverter cell, and (B) a logic threshold voltage for a decrease in input pin voltage of the first inverter cell is set to a voltage above the switching threshold voltage of the first inverter cell. Similarly, logic threshold voltages for an increase and a decrease in input pin voltage of the second inverter cell are determined. Additionally, in order to guarantee that an intercell wire delay is always evaluated to be positive, logic threshold voltages for an output pin voltage of the first inverter cell are made to agree with the logic threshold voltages for the input pin voltage of the second inverter cell.

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Osaka, Japan

Yasuhiro Tomita