International Business Machines Corporation

Yasuhiro Takase

Hiroshi Uchiike

Takashi Kuroda

Katsuhiko Katoh

Masayuki Murakami

Tatsuya Sakai

Toshio Kanai

The present invention provides a data storage device comprising a disk storage medium containing user data in a plurality of sectors, a head for writing or reading the user data and error correcting means for correcting an error that occurs in the user data during the reading process. The error correcting means comprises a syndrome generator for generating syndromes on the basis of the user data contained in predetermined sectors, registers for storing the syndromes generated and an exclusive OR circuit for exclusive ORing the values stored in the registers.

Error correction method and apparatus for data storage device

A data storage device comprising a disk storage medium containing user data in a plurality of sectors wherein each of the plurality of sectors comprises a subdivision of a track, a head for writing or reading the user data and error correcting means for correcting an error that occurs in the user data during the reading process. The error correcting means comprises a syndrome generator for generating syndromes on the basis of the user data, a Euclid circuit, a chien search circuit and a verification circuit, and makes the error correction using a first error correcting code appended to each of a plurality of sectors and a second error correcting code appended to said sector for every block composed of a predetermined number of sectors.

Data storage method and data storage device

The exclusive OR (XOR) of user data (sector), user data (sector)and user data (sector)is taken to have the virtual user data, thereby giving rise to a correlation of the sectorsto, and its virtual user data is appended with Chaving a greater error correction capability than C, whereby an error uncorrectable with Cis correctable with C

Data storage device and data processing method

The present invention is a semiconductor device that includes a DRAM and an internal mask ROM that are implemented on a single integrated circuit substrate. The semiconductor further includes a terminal coupled to an external ROM and a selector for choosing an external ROM or an internal mask ROM for program code loading. If an external ROM is coupled to the aforementioned terminal, the external ROM is given precedence for use in the loading of the aforementioned program code. The control method of the present invention pertains to a semiconductor device including a DRAM, an internal mask ROM, a terminal coupled to an external ROM, a selector for choosing the first path led from the internal mask ROM or the second path led from the terminal, and a coupling determiner deciding whether or not the terminal is coupled to the external ROM. The control method includes the steps of: (a) deciding whether or not the terminal is coupled to the external ROM; (b) selecting a first path when a terminal is not coupled to the external ROM or a second path when the terminal is coupled to the external ROM; and (c) loading a program code from either the internal mask ROM or the external ROM.

INTEGRATED CIRCUIT AND METHOD OF AUTOMATICALLY SELECTING AN INTERNAL OR AN EXTERNAL NON-VOLATILE MEMORY AS A SOURCE OF PROGRAM CODE RESPONSIVE TO PRESENCE OR ABSENCE OF THE EXTERNAL NON-VOLATILE MEMORY

A power consumption reduction circuit includes a clock frequency downconverting circuit. The clock frequency downconverting circuit downconverts a frequency of a CK signal, which is inputted, when a POR signal inputted is asserted, and outputs the CK signal to an IC selection circuit. In addition, if the POR signal inputted is negated, the clock frequency downconverting circuit outputs the CK signal inputted as it is to the IC selection circuit. A signal outputted from the clock frequency downconverting circuit is supplied to a plurality of ICs through the IC selection circuit.

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Zama, Japan

Yasuhiro Takase