Micron Technology Incorporated

Yasuhiro Takai

Martin Brox

Maksim Kuzmenka

Mani Balakrishnan

Yutaka Uemura

A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

Phase lock circuitry using frequency detection

Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.

Phase locked loop circuit

An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.

Systems and methods for a centralized command address input buffer

Apparatuses including a data input circuit of a semiconductor device are described. An example apparatus includes a first transistor that receives a reference voltage, a second transistor that receives an input signal, cross-couple type transistors, diode-connect type transistors and resistors. The cross-couple type resistors include a third transistor having a gate coupled to a drain of the second transistor, and a fourth transistor having a gate coupled to a drain of the first transistor. The diode-connect type transistors include a fifth transistor having a drain coupled to a drain of the third transistor, and a sixth transistor having a drain coupled to a drain of the fourth transistor. The resistors include a first resistor coupled between a gate and the drain of the fifth transistor and a second resistor coupled between a gate and the drain of the sixth transistor.

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Sagamihara, Japan

Yasuhiro Takai