Fujitsu Corporation

Yasuhiro Takada

Nobumi Kodama

Yoshihiro Takemae

Kimiaki Sato

Makoto Yanagisawa

Shinya Fujioka

Masao Nakano

Shigeki Nozaki

Yoshiaki Okuyama

Takashi Horii

Hatsuo Miyahara

Tatsuhiro Watanabe

Satoshi Momozono

Takeo Takematsu

A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

Semiconductor memory and burn-in test method of semiconductor memory

A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.

Semiconductor memory device with a detection circuit to detect word line

In a semiconductor integrated circuit having first and second power supply lines for receiving a power supply voltage, an external input terminal for receiving an input signal, and a high voltage detection circuit for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage, the high voltage detection circuit comprises an input circuit connected to the external input terminal for generating circuit for generating a reference voltage; and a differential voltage amplifier connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied, the input circuit comprising; a level shift element connected to the external input terminal for providing the detection voltage; an impedance element connected between the level shift element and the second power supply line; and a leak current compensating element connected between the first power supply line and the level shift element for allowing a current to flow from the first power supply line through the leak current compensating element and the impedance element to the second power supply line when the high voltage is not applied to the external input terminal.

Semiconductor integrated circuit having function for switching

Growing community of inventors

Yokohama, Japan

Yasuhiro Takada