Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Shibaura Denki Kabushiki Kaisha Horikawa Cho Sai Wia Kawasaki

Yasuhiro Sugimoto

Hiroyuki Hara

Hisashi Sugiyama

Kazunori Tsugaru

Satoshi Mizoguchi

Michinori Nakamura

Yukio Kamatani

Shoichi Shimizu

Hiromi Mafune

Tetsu Nagamatsu

Shozo Nitta

Takeshi Sugoh

Shouzou Nitta

This invention discloses a constant voltage circuit including a bandgap circuit connected between a ground voltage and a source voltage, a transistor, the collector of which is connected to the collector of a negative feedback transistor for supplying a voltage of a base-emitter path to the other terminal of a resistor having one terminal connected to an output terminal of the bandgap circuit, and the base of which is connected to a voltage source free from variations in source voltage, and a resistor connected between the emitter of the transistor and the source voltage.

Constant voltage circuit

This invention discloses a static random access memory having a plurality of data writing/reading ports, including a pair of bit lines of a first port and a pair of bit lines of second port, a memory cell for storing and outputting data, a bit line sense amplifier for sensing and amplifying data from the memory cell, a first transfer gate arranged between a first node of the memory cell and a first bit line of the first port, a second transfer gate arranged between a second node of the memory cell and the second bit line of the first port, a third transfer gate arranged between the first node of the memory cell and the first bit line of the second port, and a fourth transfer gate arranged between the second node of the memory cell and the second bit line of the second port, a drain source transconductance of the third and fourth transfer gates being larger than a drain-source transconductance of the first and second transfer gates, first and second base ground circuits, arranged between the bit line sense amplifier of the first port and the first bit line and between the bit line sense amplifier of the first port and the second bit line, for clamping a potential of each of the first pair of bit lines to a predetermined level upon start of a read operation of data.

Semiconductor memory having a plurality of ports

A Bi-CMOS logic gate circuit according to the present invention comprises a complementary Bi-CMOS output circuit at the output stage composed of a first-polarity bipolar transistor and a second-polarity bipolar transistor, and a level compensation circuit, provided between the input and output terminals of the Bi-CMOS output circuit, which compensates for each forward-bias voltage between the base and emitter of the first-polarity and second-polarity bipolar transistors. This arrangement allows the Bi-CMOS output circuit to swing the output voltage from the voltage of the high-voltage supply to that of the low-voltage supply at the output stage, previously smaller in the amplitude by the amount equal to the sum of the base-emitter voltage of two bipolar transistors.

Bi-CMOS logic gate circuits for low-voltage semiconductor integrated

In an ECL circuit comprising a differential type switching circuit having first and second output terminals, a first transistor connected to a first power source, a second transistor connected to a second power source, and a capacitor connected between the second output terminal of the switching circuit and the base of the second transistor, the ECL circuit further comprises a constant current source connected between the first power source and the base of the second transistor, and an impedance connected between the base of the second transistor and the second power source. In the above ECL circuit, the base of the second transistor is biased by means of a circuit constituted by the constant current source and the impedance and the static current flowing in the second transistor can be stably maintained by using a constant current source which can be easily obtained in the prior art as the above constant current source. Further, since the base potential of the second transistor can be determined by the second power source potential of the constant current source, the power consumption can be reduced by adequately setting the second power source potential. In addition, since the base impedance of the second transistor can be set to be higher than the base impedance of the transistor Q5 in the conventional circuit shown in FIG. 1, charges injected into the base of the second transistor via the capacitor may effectively function, causing the driving ability of the second transistor to be enhanced.

ECL circuit with a reduced power active pulldown

A current switching circuit includes first and second FETs of the same channel type whose drain-source paths are commonly connected at one end and whose gates are connected to receive logic input signals in an inverted relation, and the other end of the drain-source path of the first FET is connected to an external circuit. The current switching circuit further includes a bipolar transistor connected to a commonly connected node between the drain-source paths of the first and second FETs.

BiCMOS current switching circuit having a plurality of resistors of a

A P-channel MOSFET includes a gate for receiving an input signal, a source connected to a power supply terminal to which a high power supply voltage is applied, and a drain connected to the base of an NPN bipolar transistor at an output stage. The collector of the bipolar transistor is connected to the power supply terminal and the emitter thereof is connected to an output terminal. An N-channel MOSFET includes a gate for receiving the input signal, a drain connected to the output terminal, and a source and a back gate both connected to the base of an NPN bipolar transistor at the output stage. The collector of the bipolar transistor is connected to the output terminal, and the emitter thereof is connected to a power supply terminal to which a power supply voltage of ground potential is applied.

BI-MOS semiconductor integrated circuit

An ECL circuit is designed such that at the beginning of the falling of the output level, the current flowing to an output terminal is rapidly led in the direction where it will be reduced, the potential of the output terminal at this time is directly detected, and a pull down transistor is controlled through a feedback loop, thus assuring high-speed operation and low power consumption. A control circuit is provided to regulate the collector current of the pull down transistor, which is used to drop the level of the potential at the output terminal. This control circuit is so designed that the base current of the pull down transistor is controlled by the operation of another, single transistor, and no capacitor which will obstruct the circuit integration is employed to drive the pull down transistor. The structure of this circuit is therefore advantageous in realizing higher integration.

ECL circuit with feedback controlled pull down in output

A semiconductor integrated circuit includes a bias voltage generating circuit and first- and second-level signal generating circuits. The bias voltage generating circuit includes a bandgap reference circuit for generating a first fixed voltage as a first bias voltage and a second fixed voltage. A second bias voltage is generated on the basis of the second fixed voltage. The second-level signal generating circuit receives a predetermined first-level signal and generates a predetermined second-level signal on the basis of the first and second bias voltages generated by the bias voltage generating circuit. The first-level signal generating circuit receives the predetermined second-level signal and generates the predetermined first-level signal on the basis of the first and second bias voltages generated by the bias voltage generating circuit.

Semiconductor integrated circuit with improved I/O structure with ECL to

According to this invention, a level converter has a pair of differential transistors operated at a negative voltage in accordance with an ECL-level input signal, and first and second output nodes are arranged between a collector of one transistor of the pair of differential transistors and a positive power source voltage. A level-converting resistor for converting an ECL-level signal to a positive level signal is inserted between the first output node and the second output node so as to output the positive level signal in accordance with an ECL-level input signal to the first output node. The emitter-collector path of a bipolar transistor is inserted between the second output node and the positive power source voltage. A clamp potential for controlling saturation of transistors constituting a TTL circuit connected to an output of the transistor is generated by a constant potential applied to the base of the transistor.

Level converter for converting ECL-level signal voltage to TTL-level

A semiconductor device is disclosed having a channelless gate array. A plurality of standard cells are formed on a gate array chip such that one of the standard cells is formed relative to the adjacent standard cell with a bipolar transistor and resistor shared, as a BiCMOS logic gate, by the mutually adjacent standard cells at one end.

Channelless gate array with a shared bipolar transistor

A logic circuit outputs state signals of seven different kinds, on the basis of first, second and third digital signals. A first composite gate circuit outputs a logical OR among the first to third digital signals as a first state signal. A first gate circuit outputs a logical OR between the second and third digital signals as a second state signal. A second composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical OR between the supplied logical AND and the third digital signal as third state signal. A third composite gate circuit is supplied with a logical OR between the first and second digital signals, and outputs a logical AND between the supplied logical OR and the third digital signal as a fifth state signal. A second gate circuit outputs a logical AND between the second and third digital signals as a sixth state signal. A fourth composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical AND between the supplied logical AND and the third digital signal as a seventh state signal. The third digital signal is output as a fourth state signal without being processed. Each of the above circuits has an emitter coupled logic structure.

Logic circuit for use in D/A converter having ECL-type gate structure

Through first and second external terminals, fixed potentials are applied to both ends of a first ladder resistor network. A second ladder resistor network is connected at one end to a second transistor. The first external terminal is connected to a first transistor through a resistor, the resistor and the resistors of the first and second ladder resistor networks being of the same kind. A positive input terminal of an operational amplifier is connected to a node between the resistor and the first transistor. A negative input terminal of the amplifier receiving a reference voltage is connected to the second external terminal. The first and second transistors are driven by the output signal of the amplifier. The amplifier cooperates with the first transistor such that a potential at the node is equal to the potential of the reference voltage. As a result, a current flowing through the resistor is proportional to a current flowing through the first ladder resistor network. Since the current, which is based on the operation of the second transistor, flows into the second ladder resistor network, the current flowing through the first transistor is proportional to a current flowing through the second ladder resistor network.

Bias circuit for a subranging analog to digital converter

This invention discloses an analog/digital converter including comparator groups in which each comparator is constituted by bipolar transistors, for comparing reference voltages with an analog input voltage, and means for obtaining a digital converted value corresponding to the analog input voltage, in accordance with comparison results of in the comparator groups.

High-precision and high-speed analog/digital converter having low power

An analog/digital converter circuit including a capacitor having a first end, to which an analog voltage is applied, and a second end, an input buffer circuit having an input terminal, connected to the second end of said capacitor, and an output terminal, a reference voltage generating circuit for generating a plurality of reference voltages having different voltage levels, a voltage comparator circuit having a plurality of voltage comparators for comparing the output voltage of the input buffer circuit with each of the reference voltages generated by the reference voltage generating circuit, and generating a digital signal corresponding to the comparison results, a decoder circuit for decoding the output of the voltage comparator circuit, and D.C. bias voltage selection/supply circuit for selecting one of the reference voltages of the reference voltage generating circuit and supplying the selected reference voltage as a D.C. bias voltage to the input terminal of the input buffer circuit.

Analog/digital converter circuit

An attenuator circuit is provided which comprises an input node, a first resistor connected at one terminal to a reference potential, a second resistor connected to the other terminal of the first resistor, a first output node which is a connection node of the first resistor and the second resistor, a third resistor connected in parallel with the series circuit of the first and second resistors and being of such a type that a resultant resistive value of the first, second and third resistors is equal to a resistive value of the first resistor, a fourth resistor connected at one terminal to a connection node of the second and third resistors and having a resistive value substantially equal to that of the second resistor, and at least one combination resistor of a ladder configuration connected between the other terminal of the fourth resistor and the input node and having a third output node as a junction of its series circuit portion.

Growing community of inventors

Yokohama, Japan

Yasuhiro Sugimoto