Hitachi, Ltd.

Other

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Yasuhiro Sugawara

Yuzuru Ohji

Misuzu Kanai

Naruhiko Nakanishi

Shinpei Iijima

Ryouichi Furukawa

Nobuyoshi Kobayashi

Masahiko Hiratani

Hirohiko Yamamoto

Akira Takamatsu

Tadanori Yoshida

Masayuki Ishizaka

Shinpei Iljima

Toshio Uemura

Yuzuru Oji

Sinpei Iijima

Koichiro Ishibashi

Toshihiko Tanaka

Norio Hasegawa

Takashi Hashimoto

Toshiaki Yamanaka

Akihiro Shimizu

Tokuo Kure

Naotaka Hashimoto

Takuya Fukuda

Eiji Takeda

Hideharu Yahata

Takashi Nishida

Hisashi Takahashi

Katsuhiko Yuura

Shoichi Kubo

Shimpei Iijima

A first silicon film is so formed as to extend along the inner surface of trenches formed in a silicon oxide film , an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode of a capacitance device can be lowered.

HSG semiconductor capacitor with migration inhibition layer

An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate and having a lower electrode , a capacity insulating film and an upper electrode . The lower electrode is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

Method of forming a semiconductor device with a capacitor including a polycrystalline tantalum oxide film dielectric

A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode a capacitor insulator and an upper electrode wherein the lower electrode is made of a conductive material containing ruthenium dioxide (RuO ) as principle ingredient and the capacitor insulator is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

Semiconductor integrated circuit device and method of manufacturing the same

A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode , a capacitor insulator and an upper electrode , wherein the lower electrode is made of a conductive material containing ruthenium dioxide (RuO ) as principle ingredient and the capacitor insulator is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

Semiconductor integrated circuit device with information storage capacitor having ruthenium dioxide lower electrode and crystallized TA2O5 capacitor insulator

Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.

Semiconductor device comprising capacitor cells, bit lines, word lines, and MOS transistors in a memory cell area over a semiconductor substrate

An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate and having a lower electrode a capacity insulating film and an upper electrode The lower electrode is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

Method of forming a semiconductor device including a capacitor with tantalum oxide (Ta2O5)

A first silicon film is so formed as to extend along the inner surface of trenches formed in a silicon oxide film an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode of a capacitance device can be lowered.

Semiconductor device and method of fabricating the same

In an animation generating method wherein a component of an apparatus to be designed is defined by an instance of an object-oriented program and a figure is allocated to said instance on a computer, and further an animation method for varying a representation of said figure in connection with the operation of the instance is interactively generated, a designation is made of either a slot of said instance, or a method argument of a method effected to said instance, and further a designation is made of a figure attribute of a figure to be changed in an animation representation. In response to this, an animation method for changing the figure attribute is automatically generated with refererence to the slot of the instance, or the method argument of the method effected to the instance.

Animation generating method in a design supporting system

There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Semiconductor memory device having static random access memory

Growing community of inventors

Akishima, Japan

Yasuhiro Sugawara