Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Yasuhiro Shimamoto

Digh Hisamoto

Masahiko Hiratani

Hiroshi Miki

Toshiyuki Mine

Tetsuya Ishimaru

Toshihide Nabatame

Yuichi Matsui

Hirotaka Hamamura

Tsuyoshi Arigane

Kan Yasui

Yoshihisa Fujisaki

Keiko Kushida

Yoshitaka Nakamura

Kazuyoshi Torii

Shinichiro Takatani

Naoki Tega

Itaru Yanagi

Hiromi Nakai

Daisuke Okada

Masao Inoue

Jiro Yugami

Masaharu Mizutani

Kenichi Akita

Keisuke Kuwahara

Shinichiro Kimura

Shinichi Saito

Tomoyuki Hamada

Yuki Mori

Shimpei Tsujikawa

Yutaka Okuyama

Hiroyuki Okino

Yasufumi Morimoto

Katsunori Obata

Satoshi Yamamoto

Shinpei Iijima

Ryuta Tsuchiya

Koichi Toba

Daisuke Matsumoto

Hiroyuki Yoshimoto

Hiroshi Sakuma

Yasunobu Aoki

Toshio Ando

Yasafumi Morimoto

In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p'-type polysilicon film with a high impurity concentration deposited thereon.

Semiconductor storage device and manufacturing method thereof

The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.

MOS field effect transistor

A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer () disposed on an upper portion of a first surface side of an SiC substrate (); a p body layer () which surrounds the source layer and has a channel region; an n-type drift layer () which is in contact with the p body layer (); a gate electrode () which is disposed on an upper portion of the channel region via a gate insulating film; and a first player () which is disposed in the p body layer (), extends to a portion below the nsource layer (), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (). In this manner, since the first player () is formed in the middle of the p body layer (), it is possible to reduce the diffusion resistance of the p body layer (). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.

Semiconductor device and manufacturing method of semiconductor device

In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage.

Field effect silicon carbide transistor

A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.

Nonvolatile semiconductor device and method of manufacturing the same

A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.

Silicon carbide semiconductor device and manufacturing method thereof

A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.

4h-SiC semiconductor element and semiconductor device

A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.

Silicon carbide semiconductor device

Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1&#xd7;10to 5&#xd7;10atoms/cmare contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2&#xd7;10/cm.

Semiconductor device and manufacturing method of the same

In a non-volatile memory, writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film, which serves as a charge accumulation layer. The gate electrode of a memory cell has a laminated structure made of a plurality of polysilicon films with different impurity concentrations. In a two-layered structure the gate electrode has a p-type polysilicon film with a low impurity concentration and a p-type polysilicon film with a high impurity concentration deposited thereon. Holes are injected into the charge accumulation layer from the gate electrode.

A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1&#xd7;10to 5&#xd7;10atoms/cm.

Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (ntype semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (ntype semiconductor region) is also electrically connected to the well (p type semiconductor region).

Non-volatile semiconductor memory device and method of manufacturing the same

In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p-type polysilicon film with a high impurity concentration deposited thereon.

Nonvolatile semiconductor device including a field effect transistor having a charge storage layer of predetermined length

Growing community of inventors

Tokorozawa, Japan

Yasuhiro Shimamoto