Fujitsu Corporation

Yasuhiro Ooba

Syuji Takada

Masao Nakano

Kenichi Kawarai

Yuichi Uzawa

Takeshi Toyoyama

Masayuki Tanaka

Satoshi Tanaka

Naotoshi Watanabe

Naoki Matsuoka

Hiroshi Tomonaga

Yukio Suda

Hichiro Hayami

Shuji Takada

Shiuji Sakakura

Masayuki Horie

Takeshi Terada

Yasutaka Ohno

Yukihiro Kikuchi

A protocol converting unit stores identification information for identifying a transfer path for data in a second network and a transmission source address specified in a packet in a corresponding manner. A failure detecting unit detects a transfer path in which a failure has occurred in the second network. A dummy-packet transmitting unit obtains a transmission source address corresponding to identification information of the transfer path in which the failure is detected, and transmits a dummy packet in which the obtained transmission source address is specified as the transmission source address to a first network.

Transmitting apparatus and method for maintaining learned information

In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.

Frame buffer monitoring method and device

A data relay apparatus in which a search request command can be inputted efficiently to a content addressable/associative memory device. When a packet is inputted, a network processor generates a search request and passes it to the content addressable/associative memory device. Then the content addressable/associative memory device analyzes the structure of the search request and generates a plurality of search conditions. The content addressable/associative memory device makes a search according to each search condition and outputs a memory address corresponding to a detected piece of information to be searched to a memory device. The memory device passes a candidate search result corresponding to the memory address to the network processor as a search result.

Data relay apparatus, content addressable/associative memory device, and content addressable/associative memory device use information search method

A transmission rate monitoring apparatus capable of promptly detecting the average transmission rate of data transmitted on a transmission channel. Data is received on the transmission channel, and a desired average transmission rate is set with respect to a predetermined time period. The amount of data received is measured and data is accepted or discarded in accordance with the data amount measured within the predetermined time period and the average transmission rate.

Transmission rate monitoring apparatus and method

A common buffer memory control apparatus controls a common buffer memory which is used to store message data items each of which is divided into a plurality of cells based on an asynchronous transfer mode. The common buffer memory control apparatus includes a free block management table for managing whether each of blocks into which the common buffer memory divided is free or used, a block selecting unit for selecting a block of the common buffer memory which is free with reference to the free block management table, and a cell writing control unit for controlling a write operation for cells of a single message data item so that the respective cells of the single message data item are written in the block, selected by the block selecting means, of the common buffer memory.

Common buffer memory control apparatus

The present invention relates to a packet transfer communication device. More particularly, the present invention relates to a congestion control unit designed to handle communication at high speed by reducing a load of congestion processing conducted in a core router and an edge router. The congestion control unit includes a packet discarding judgment section that conducts congestion control by a packet discarding judgment based on a smooth queue length which is a quantity of accumulated data composed of a difference between a quantity of input data and a quantity of output data at each predetermined period in a smooth queue length calculating section.

Congestion control unit

A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.

Data control device and an ATM control device

The invention relates to a flow controlling apparatus provided in a node of a packet routing network, the flow controlling apparatus performing a rate-based congestion control on packets supplied via an incoming line as well as buffer management. The invention also relates to a node apparatus that incorporates such a flow controlling apparatus. In the flow controlling apparatus and the node apparatus, a frequency at which individual packets belonging to the flows are to be discarded during the course of buffer management are kept, for each flow, at approximately the same value. Therefore, in a network to which the invention is applied, the transmission quality is kept uniform and the service quality is highly maintained while flexible adaptation is made to various service forms.

Flow controlling apparatus and node apparatus

An ATM layer cell processing apparatus is provided with a plurality of cell processing sections, including a plurality of OAM cell processors provided with respect to each of OAM cell types, a cell identifying section outputting cell type information by decoding header information of an arrived cell, an OAM identifying section outputting OAM identification information including OAM type information identified based on OAM cell information of a payload and the cell type information, where the cell identifying section and the OAM identifying section are provided in common with respect to the plurality of cell processing sections including the plurality of OAM cell processors, and a mechanism sending the OAM ell type information and cell data of the arrived cell to a cell processing section which is to process the arrived cell at a subsequent stage, based on the OAM identification information output from the OAM identification section.

ATM layer cell processing apparatus

A communication protocol processing unit by a multiprocessor is disclosed, and includes a first processor for performing a process demanding a real time property on a stream of communication data; and a second processor for performing a process not demanding the real time property, wherein the first processor transfers using parameters paired with the communication data to be processed to the second processor, and the second processor is structured so as to refer to the transferred communication data and parameters to process.

Communications protocol processing by real time processor off-loading operations to queue for processing by non-real time processor

A packet insertion interval control system includes a counting unit ( ), having a first bit field for managing an insertion interval of a management packet required to be cyclically inserted and a second bit field for specifying a logic path for forwarding the management packet, for executing such a counting operation as to periodically cycle the first bit field and the second bit field, and a control unit ( ) for executing control for specifying, when a count value indicated by the first bit field of the counting unit is a predetermined value, the logic path for forwarding the management packet on the basis of a count value indicated by the second bit field of the counting unit, and for inserting the management packet into the specified logic path. With this architecture, it is feasible to restrain an increase in quantity of the hardware and flexibly correspond to changes in the number of connections (number of channels) and the cell insertion interval (packet insertion interval) per communication system.

Packet insertion interval control system and packet insertion interval control method

The invention relates to a bandwidth control apparatus in ATM equipment, for inserting management cells such as OAM cells, the control apparatus being configured to secure a bandwidth for the insertion of a management cell such as an OAM cell when the need arises, while guaranteeing the service quality of user cells, thereby making effective use of network resources for a best effort service such as ABR or UBR. The bandwidth control apparatus comprises a cell insertion block - for inserting a management cell such as an OAM cell and a shaping block - for performing user cell shaping, wherein the cell insertion block - issues an empty cell request when a cell insertion request occurs, the shaping block - upon receiving the empty cell insertion request, inserts an empty cell in a user cell stream being output from a shaping buffer - and the cell insertion block - writes a management cell such as an OAM cell over the empty cell inserted on a cell highway - thus sending the management cell out on the cell highway -

Bandwidth control apparatus

An associative memory apparatus has such a structure as to reduce a load of an updating work and readily cope with an increase of the capacity. The associative memory apparatus outputs longest prefix match in only one searching operation, thereby shortening a processing time for the searching process. The apparatus comprises entry units, each of which includes a logical operating means outputting information about a bit length not masked in entry data when the entry data stored in its own entry unit coincides with bit data that is a key, and a search result outputting means outputting a search match information with respect to the search key only when the entry data stored in its own entry unit is entry data having the longest bit length not masked.

Associative memory apparatus and routing apparatus

In data insertion control technique; a plurality of buffers hold different types of data, which are to be inserted into a predetermined transmission medium and are equal in insertion priority, and a data insertion controller controls the data insertion order in which the data are to be inserted into the transmission medium by controlling the read process order in which the different types of data are to read from the buffers, based on the write process order in which the different types of data have been stored in the buffers. The result is that it is possible to realize exact data insertion in a minimum delay time.

Buffer apparatus with data insertion control function, insertion data controlling method, and data insertion apparatus with data insertion control function

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Kawasaki, Japan

Yasuhiro Ooba