Seiko Epson Corporation

Yasuhiro Oguchi

Yasuhisa Hirabayashi

Takashi Sakuda

Kazuhiko Okawa

Yoshiyuki Miyayama

Masuo Tsuji

Kensuke Torii

Kazuhiko Ohkawa

Kazuhiko Ookawa

The semiconductor integrated circuit of this invention comprises at least one first semiconductor circuit (,) that is driven on the basis of on at least one first clock signal (,). In addition, there is at least one second semiconductor circuit (,) assisting the first semiconductor circuit (,), which operates on the basis of at least one second clock signal (,) independent of the first clock signal (,) and a request from the first semiconductor circuit (,). The second semiconductor circuit (,) comprises a halt means (,) that causes the second clock signal (,) to halt if necessary. This makes it possible to halt the second clock signal (,), thus halting the operation of the second semiconductor circuit (,).

Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the same

Semiconductor device

Master slice semiconductor integrated circuit with output drive current

In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its associated power branch-off member and the respective power line.

Master slice integrated circuit device

Disclosed is a semiconductor device having complementary metal insulator semiconductor field-effect transistors (MISFETs) in which a plurality of basic cells having N-channel MOSs and P-channel MOSs are disposed. In this semiconductor device, a sub MISFET is disposed adjacently to a stopper layer in a region adjacent to other basic cell. An element such as a transmission gate composed of a single element can be actualized by use of the sub-MISFET. In the semiconductor device of this invention, a working efficiency thereof is improved. A response velocity of the P-channel MOS can also be improved using the sub-MISFET. A numerical quantity of the basic cells constituting a circuit can be reduced, resulting in a reduction in parasitic capacity. An operating time of the circuit is thereby decreased.

A semiconductor device assembly composed of a plurality of unit semiconductor devices formed into a logic circuit by selective connection among elements in the unit devices and among the unit devices. Each of the unit devices includes at least a first insulated-gate type field-effect transistor of a first conductivity type and a second insulated-gate type field-effect transistor of a second conductivity type which is disposed adjacent to the first transistor and has a gate electrode separated from a gate electrode of the first transistor. The gate electrodes of the respective transistors have at least a gate terminal portion at the side adjacent to each other, and the gate terminal portion of the first field-effect transistor has at least a first wire connecting location and a second wire connecting location. By using the second wire connecting location, wiring in and among the unit devices can be carried out via the shortest aluminum wires of a first layer, so that the wiring feasibility can be enhanced.

Growing community of inventors

Suwa, Japan

Yasuhiro Oguchi