Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Yasuhiro Nojiri

Hiroyuki Fukumizu

Shigeki Kobayashi

Masaki Yamato

Takeshi Yamaguchi

Tsukasa Nakai

Motoya Kishida

Kazuhiko Yamamoto

Yasuhiro Satoh

Shuichi Kuboi

Yoshio Ozawa

Ichiro Mizushima

Katsuyuki Sekine

Kei Watanabe

Shinichi Nakao

Takuya Konno

Hideo Eto

Akiko Nomachi

Makoto Saito

Kazuyuki Yahiro

Kenichi Ootsuka

Masanobu Baba

Kazuhito Nishitani

Noriko Bota

Masayuki Takata

A semiconductor device according to an embodiment includes a memory cell array and a drive circuit section. The memory cell array includes memory cells. The drive circuit section adapted to control a driving voltage to be supplied to the memory cells. The memory cells each including a first variable resistance film and a second variable resistance film connected in series to the first variable resistance film. The driving voltage of the second variable resistance film is different from the driving voltage of the first variable resistance film.

Variable resistance memory

A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.

Semiconductor memory device

3D semiconductor memory device having variable resistance memory elements

According to one embodiment, an electrostatic chuck comprises a mount plate, a first layer, and a second layer. The first layer includes a heater. The second layer is provided between the mount plate and the first layer. The second layer transmits heat from the heater to the mount plate. The second layer includes a compressive attachment portion. The compressive attachment portion is formed at the outer edge. The face on the mount plate side of the compressive attachment portion is compressed and attached to the mount plate. The face on the first layer side of the compressive attachment portion is compressed and attached to the first layer.

Electrostatic chuck, mount plate support, and manufacturing method of electrostatic chuck

Semiconductor memory device having a variable resistance layer serving as a memory layer

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.

Semiconductor memory device with a memory cell block including a block film

A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory layers; and a control unit configured to control a voltage applied to the memory cell array. Each of the memory layers comprises a first line and a second line, and further includes a memory cell disposed between the first line and the second line and including a variable resistance element. The control unit is configured to, when executing a forming operation on the memory cell array, execute the forming operation sequentially on the plurality of memory layers. The forming operation is executed sequentially on the memory layers in ascending order of a magnitude of a non-selected current flowing in a non-selected memory cell during the forming operation.

Nonvolatile semiconductor memory device and method of forming same

A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second electrode is configured by a P type semiconductor. The control unit, when performing a setting operation of a memory cell, applies a voltage such that a current flows in a direction from the first electrode toward the second electrode.

A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.

According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type.

Nonvolatile memory device

First conductive layers extend in a first direction horizontal to a substrate as a longitudinal direction, and are stacked in a direction perpendicular to a substrate. An interlayer insulating layer is provided between the first conductive layers. The variable resistance layers functioning as a variable resistance element are formed continuously on the side surfaces of the first conductive layers and the interlayer insulating layer. A columnar conductive layer is provided on the side surfaces of the first conductive layers and the interlayer insulating layer via the variable resistance layers. First side surfaces of the first conductive layers are recessed from a second side surface of the interlayer insulating layer in the direction away from the columnar conductive layers.

Non-volatile semiconductor memory device

A diode layer includes a first impurity semiconductor layer that includes a first impurity acting as an acceptor and a second impurity semiconductor layer that includes a second impurity acting as a donor. One end of a first electrode layer contacts the diode layer. One end of a polysilicon layer contacts the other end of the first electrode layer. One end of a variable resistance layer contacts the other end of the polysilicon layer and is able to change a resistance value. A second electrode layer contacts the other end of the variable resistance layer. At least one of a first area and a second area contains a third impurity. The first area includes one end of the polysilicon layer, the second area includes the other end of the polysilicon layer. The third impurity differs from the first impurity and the second impurity.

Semiconductor storage device including a diode and a variable resistance element

According to one embodiment, a memory cell includes a resistance change layer, an upper electrode layer, a lower electrode layer, a diode layer, a first oxide film, and a second oxide film. The upper electrode layer is arranged above the resistance change layer. The lower electrode layer is arranged below the resistance change layer. The diode layer is arranged above the upper electrode layer or below the lower electrode layer. The first oxide film exists on a side wall of at least one electrode layer of the upper electrode layer or the lower electrode layer. The second oxide film exists on a side wall of the diode layer. The film thickness of the first oxide film is thicker than a film thickness of the second oxide film.

Non-volatile semiconductor storage device and manufacturing method of non-volatile semiconductor storage device

A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.

Nonvolatile semiconductor memory device

According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.

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Yokohama, Japan

Yasuhiro Nojiri