Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Engineering Co., Ltd.

Other

Renesas Electronics Corporation

East Japan Railway Company

Hitachi Information & Control Solutions, Ltd.

Hitachi Information Control Systems, Inc.

Yasuhiro Nakatsuka

Takashi Hotta

Tadaaki Bandoh

Koyo Katsura

Shigeru Matsuo

Shigeya Tanaka

Masahiro Iwamura

Hideo Maejima

Kazuo Kato

Kenichi Kurosawa

Kozaburo Kurita

Kotaro Shimamura

Yuichiro Morita

Kazushige Yamagishi

Jun Satoh

Keisuke Nakashima

Hiromichi Yamada

Tatsuki Inuzuka

Hiroshi Arita

Toshimichi Minowa

Nobuyasu Kanekawa

Masatoshi Hoshino

Kohei Sakurai

Yoshiaki Takahashi

Shoji Sasaki

Takanaga Yamazaki

Kentaro Yoshimura

Atsushi Nakamura

Masahiko Saito

Yoshiki Kobayashi

Yuichi Abe

Masaya Ichinose

Ryo Fujita

Teppei Hirotsu

Jun Sato

Tetsuya Shimomura

Sin-ichi Sinoda

Tomoaki Aoki

Takashi Sone

Masahisa Narita

Hidehito Takewa

Takeshi Takemoto

Yasuwo Watanabe

Toshio Doi

Kunihiko Tsunedomi

Masanori Miyoshi

Yutaka Okada

Manabu Jyou

Yoshihiro Tanaka

Kenji Furuhashi

Dai Fujii

Tatsuki Inuduka

Masanobu Tanaka

Ichiro Iimura

Kei Ouchi

Toshinobu Kanai

Akira Bando

Setsuo Arita

Kazuyoshi Koga

Masahiko Honda

Naomi Sato

Yoshikazu Ishii

Yasuhiro Kiyofuji

Nao Saito

Takeshi Kataoka

Mitsuru Soga

Yuji Ichinose

Yasuhiro Imazu

Jun Narushima

Yoshiki Fujioka

Osamu Sakuchi

Yuuichi Abe

Toshihiko Usui

Masaki Uchita

Rikiya Inoue

Daisuke Sinma

A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.

Vehicle control system

Feeder sections to be a target of interchange are to be expanded in order to improve the effect of power interchange between feeders. A control device for railway power conditioner is connected to a first feeder connected to a load side of a transformer in a first railway substation including a transformer receiving power from a power grid, and a second feeder connected to a load side of a transformer in a second railway substation including a transformer receiving power from a power grid, and decides an amount of power interchanged between the first and second feeders. The control device decides the amount of power interchanged between the first and second feeders, using the received power in the first railway substation and power on the first feeder, and the received power in the second railway substation and power on the second feeder.

Control device for railway power conditioner and control system for railway power conditioner

A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

Apparatus for calculating and prefetching a branch target address

A transmit packet generated by a CPUis held in a buffer(). From among packets received from Ethernet(), a packet, a destination of which is a communication device, is held in the buffer(). A packet which should be transmitted is transmitted from a transfer judging circuitto Ethernetorthrough a MAC unitor. If a transfer judging circuitjudges a packet from the Ethernetto be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernetthrough MAC. If a usage rate of a transferring FIFO buffer() exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer() on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernetorin preference to the transmit packet. This prevents a transfer buffer means from overflowing.

Packet communication device, packet communication system, packet communication module, data processor, and data transfer system

Packet communication device, packet communication system, packet communication system, packet communication module, data processor, and data transfer system

The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion information for specifying the start address of each group and compressed code type information for specifying the code length of each compressed code contained in a group are stored in a memory, and by enabling a corresponding compressed code address to be calculated from a code address output by a CPU, code compression that is favorable for a micro controller or other embedded system is realized.

Micro controller for decompressing and compressing variable length codes via a compressed code dictionary

Using a network in which one master station modemand multiple slave station modemare physically connected by rudder connection or bus connection with a telecommunication line, the measurement result of the S/N ratio between the master station and slave stations is once collected in the master station at the initialization stage, pairs of the modulation method, by which all modems can demodulate at high probability, and transmission voltage are calculated based on this data, and the calculation is transmitted to all slave stations; and at a normal transmission stage, information regarding the coordination and control of the network is transmitted in accordance with this setting. Thus, one-to-multi communication is realized, guaranteeing an access right.

Control and monitoring telecommunication system and method of setting a modulation method

The basic section of the multimedia data-processing system includes a CPU, an image display unit, a unified memory, a system bus, and devices, andconnected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unitand display control unit. Main storage areaand display areaare stored within the unified memory. Unified memory portfor connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Memory access methods in a unified memory system

A packet communication apparatus capable of performing packet conversion at high speed for packet transfer or packet transmission/reception has: a packet conversion unit for performing packet conversion for a reception packet received at a plurality of communication units and for a transmission packet to be transmitted from the plurality of communication units; and a transfer control unit for outputting, when the reception packet received by the communication unit is judged as a the transfer packet, the reception packet to a transfer buffer, for outputting the transmission packet to the communication unit corresponding to the communication object at a destination of the transmission packet generated by a packet generating and processing unit, and for outputting the transfer packet to the communication unit corresponding to the communication object at a destination of the transfer packet stored in the transfer buffer.

Packet communication apparatus

A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memoryis generated from the CPU, the memory controllerholds it once, requests the display controllerto stop the access to the memorywhich is in execution, when data to the access executed already is transferred from the memory, holds it, and transfers the access request from the CPU buswhich is held by the memory. When the access from the CPU busends, the memory controllerrestarts the access stopped in the display controllerand passes the held data to the display controller

Data processor having unified memory architecture using register to optimize memory access

In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Graphics drawing device and method

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal Kwhich is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal Kand the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.

Information processor and information processing system utilizing interface for synchronizing clock signal

Growing community of inventors

Tokai, Japan

Yasuhiro Nakatsuka