Matsushita Electric Industrial Co., Ltd.

Yasuhiro Nakakura

Senichi Furutani

Shouichi Yoshizaki

A convolutional interleaver performs convolutional inerleaving for a data group in which the input/output data width is b bits, the depth, i.e., the number of data in bit width units, is m, the number of channels is n, and the maximum channel number is C (n&equals;integer satisfying the relation 0&lE;n&lE;C, b,m,C&equals;natural number). This interleaver includes a delay unit comprising first and second delay units and performing a delay of n&tgr; for data of the n-th channel (T&equals;a predetermined amount of delay, T>0) The first delay unit performs a delay of is (S&equals;a predetermined amount of delay, 0<S&lE;T) for the i-th group amongst groups into which all the channels are grouped such that each group comprises at most k channels, and the second delay unit performs a delay equivalent to a deficiency in the delay of the first delay unit for the delay of nT to be given to the data of the n-th channel. Therefore, delays to be commonly generated between channels in each group are generated together by the first delay unit, and delays including differences in delays between the channels are individually generated by the second delay unit, whereby control and structure of the delay means can be simplified.

Convolutional interleaver, convolutional deinterleaver, convolutional interleaving method, and convolutional deinterleaving method

The present invention discloses an integrated circuit for use in pipeline processing formed by a plurality of stages. Data is latched by a first latch. A first logic element receives the output of the first latch and processes it. A second latch receives the output of the first logic element and processes it. A second logic element receives the output of the second latch and processes it. If the processing time of the first logic element is longer than that of the second logic element, a clock signal being applied to the second latch which gives its output to the second logic element is delayed by a delay element a given delay time. Such a given delay time is determined to be below the minimum delay time of the first logic element. Cycles per pipeline stage are variable. With a clock cycle shorter than the processing time of one of the first and second logic elements that has a longer processing time than the other, pipeline processing becomes possible. Therefore, data processing time shortens.

Integrated circuit for pipeline data processing

In the case where an external signal line is driven by a circuit other than an output circuit with a voltage higher than an on-chip power-source voltage, if an output transistor is activated in the output state immediately after the driving of the external signal line by the above other circuit was cancelled, a voltage equal to or higher than the breakdown voltage of an oxide film of a transistor composing the output circuit is applied thereto. To prevent this, there is provided a voltage detecting means for detecting a voltage value of the above external signal line being higher than a value in the vicinity of the internal power-source voltage and generating a detection signal, which inhibits the activation of the output transistor. Consequently, in the output circuit of an LSI fabricated using submicron design rules, the application of a voltage equal to or higher than the breakdown voltage of an oxide film of each of the transistors composing the output circuit is prevented, resulting in increased reliability of the output circuit.

Output circuit with high output voltage protection means

Provided on the periphery of a semiconductor chip are a clock input pad 10 and a clock driver 11. Clock pulse generators 13A to 13G are provided to functional blocks 12A to 12F. A clock signal line 14, through which clock signals are transmitted to the clock pulse generators 13A to 13G, is composed of a first clock line 14a extending from the clock driver 14 to the center of the semiconductor chip, and a plurality of second clock lines branching, at the center of the semiconductor chip, from the leading end of the first clock line to extend to the clock pulse generators 13A to 13G respectively.

Semiconductor integrated circuit

An addition apparatus adds together two numbers while detecting one of a plurality (n) of possible round-off positions and executing round-off at that position simultaneously with adding together the numbers. The apparatus is divided into a plurality of circuit sections. In a first section, two lowest-significance portions of the two numbers are added together in each of n parallel adder circuits while executing round-off processing at respectively different bit positions in each of the adder circuits. In each of subsequent sections, portions of increasing significance of the two input numbers are added together in a first parallel adder to which a '1' state input carry is applied and a second parallel adder in which a '0' state carry is supplied, and in each section, n section carry signals are--generated in accordance with carry outputs produced from the adders of that section and respective section carry signals produced from the preceding section. A control signal for selecting the output sum from one of the parallel adders of the lowest-significance section and thereby determining the round-off position is generated based on a combination of carry signals supplied to the highest-significance circuit section and MSB signals produced from the two parallel adders of that section.

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Osaka, Japan

Yasuhiro Nakakura