Socionext Inc.

Yasuhiro Majima

Takashi Miyazaki

Shunsuke Hirano

Kenta Aruga

Daisuke Kimura

Shunichiro Masaki

A processing circuit includes: a clock generating circuit configured to generate, based on a reference clock signal and a frequency division ratio, a first clock signal; a frequency dividing and delay circuit configured to generate a second clock signal to have a first phase difference with the reference clock signal by dividing the frequency of the first clock signal and delaying the first clock signal based on a phase shift set signal and the frequency division ratio; an analog-to-digital converter circuit configured to convert an analog signal into a digital signal based on the first clock signal and a conversion trigger signal indicating a sampling period and a conversion period; and a control circuit configured to generate the conversion trigger signal to have the same cycle as the second clock signal based on the frequency division ratio and the first clock signal.

Growing community of inventors

Kanagawa, Japan

Yasuhiro Majima