Mitsubishi Denki Kabushiki Kaisha

Yasuhiro Kouro

Kenji Kohda

Tsuyoshi Toyama

Hiroyasu Makihara

Masayuki Yamashita

Satoru Tamada

Tatsuya Saeki

Tatsuki Furusho

The inventive flash memory comprises a memory cell array including nonvolatile memory cells and a control CPU controlling data writing, reading and erasing in the memory cell array and a multivalued flag part. The multivalued flag part stores a value indicating whether data written in any memory cell is binary data or multivalued data. The data can be read in a binary read sequence for the binary data or a multivalued read sequence for the multivalued data due to the value of the multivalued flag part.

Nonvolatile semiconductor memory device having structure storing multivalued data and data storage system comprising the nonvolatile semiconductor memory device

A read only semiconductor memory device includes a plurality of address coincidence detecting circuits, each of which has a specific address region assigned thereto and generates an address coincidence detecting signal when an input address signal designates an address in the assigned region. A priority circuit determines a priority order among the plurality of address coincidence detection signals from the plurality of coincidence detecting circuits. In accordance with a signal to which priority is given by the priority circuit, a data output terminal receives memory cell data read from a memory array or is fixed at a predetermined logical level. With respect to a memory address region containing a succession of only data of logic '1' or '0' (that is, a region with all '1's' or '0's'), data of a logical level predetermined by a switching circuit is output to the data output terminal. For this memory address region, fixed data, which is not read from the memory array, is outputted. Therefore, a defective bit in this memory address region can be repaired efficiently, resulting in a high product yield of the read only semiconductor memory device.

Read only type semiconductor memory device including address coincidence

An improved flash EEPROM with a sense amplifier having a sensing characteristics suitable for sensing a data signal under an externally applied supply voltage Vcc in a lower range, and a sense amplifier having a sensing characteristics suitable for sensing a data signal under the supply voltage Vcc in a higher range. A Vcc level detecting device detects in which range the supply voltage Vcc is in, soasto selectively enable one of sense amplifiers. Since the data signal is amplified using the sense amplifier having the optimum sensing characteristics in accordance with the level of the supply voltage, the stored data can be accurately read.

Semiconductor memory device capable of correct reading of data under

In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a normal power supply potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a high potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

Buffer circuit used in a semiconductor device operating by different

A memory cell array (100) of an EPROM includes a first data memory region (1a), a second data memory region (1b), a 2M code memory line (2a) and a 1M code memory line (2b). When both the first and the second data memory regions (1a, 1b) are normal, the EPROM may be used as a 2M bit EPROM, in which case a device code indicating that the EPROM is a 2M bit EPROM is read out from the 2M code memory line (2a). When a defective portion is present in one of the first and the second data memory regions (1a, 1b), the EPROM may be used as a 1M bit EPROM, in which case a device code indicating that the EPROM is a 1M bit EPROM is read out from the 1M code memory line (2b).

Semiconductor memory device having means for repairing the memory device

In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a high potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a normal power supply potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

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Hyogo, Japan

Yasuhiro Kouro