Nec Electronics Corporation

Nuvoton Technology Corporation Japan

Yasuhiro Kosaka

Kazuaki Sogawa

Takeshi Sowa

Nobuo Shimizu

Yoshihisa Fujimori

A solid-state imaging device includes a pixel array that is quadrilateral and includes pixels arranged in rows and columns, where each of the pixels accumulates an electric charge resulting from photoelectric conversion. The pixel array includes: a first area including first pixels for obtaining a captured image; and a second area including a second pixel for individually identifying the solid-state imaging device. The second area is provided in the vicinity of at least one corner among four corners of the pixel array, where the vicinity is a range of a predetermined number of pixels away from the at least one corner. The second pixel includes circuit elements or optical elements different from circuit elements or optical elements in each of the first pixels.

Solid-state imaging device and imaging apparatus

In an apparatus including a shift register adapted to pass a start signal therethrough in synchronization with a clock signal of a large amplitude level to sequentially generate a plurality of latch signals, a data register adapted to latch sequential data signals of the large amplitude level in synchronization with the latch signals, and a data latch circuit adapted to latch all the sequential data signals latched in the data register in synchronization with a strobe signal, a receiver converts differential clock signals of a small amplitude level into the clock signal of the large amplitude level from a timing of generation of the strobe signal to a timing of completion of latching all the sequential data signals in the data register, and transmits the clock signal of the large amplitude level to the shift register, and also, converts differential data signals of the small amplitude level into the sequential data signals from a timing of generation of the start signal to the timing of completion of latching all the sequential data signals in the data register and transmits the sequential data signals to the data register.

Apparatus for inputting clock signal and data signals of small amplitude level with start timing of inputting clock signal ahead of that of inputting data signals

A horizontal driver in a LCD driver includes a D/A converter having a PROM decoder block and an NROM decoder block for driving a LCD panel in a dot reversible driving scheme. Each data line receives alternately a gray-scale signal having a positive polarity generated by a PROM decoder and a gray-scale signal having a negative polarity generated by an NROM decoder, and an odd-numbered data line and an even-numbered data line receive gray-scale signals having opposite polarities. The order of the decoders is matched by a switching block with the order of the data lines by switching the display data and the gray-scale signals.

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Shiga, Japan

Yasuhiro Kosaka