Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Other

Morishita Jintan Co., Ltd.

Konishi, Yasuhiro

Yasuhiro Konishi

Katsumi Dosaka

Masaki Kumanoya

Hisashi Iwamoto

Akira Yamazaki

Kouji Hayano

Takahiro Komatsu

Hideaki Abe

Yasuhiro Ishizuka

Katsumitsu Himukashi

Hideshi Miyatake

Tsukasa Saiki

Hideto Hidaka

Seiji Sawada

Hiroyuki Yamasaki

Yoshinori Inoue

Kazuyasu Fujishima

Takayuki Miyamoto

Yuto Ikeda

Yasumitsu Murai

Takashi Araki

Youichi Tobita

Takeshi Kajimoto

Kazuhiro Tsukamoto

Masaki Shimoda

Kiyohiro Furutani

Takashi Kono

Takeshi Hamamoto

Naoya Watanabe

Takashi Kubo

Mikio Asakura

Hirofumi Shinohara

Masaru Haraguchi

Tetsushi Tanizaki

Tetsuo Kato

Ryosei Kamaguchi

Mikio Sakurai

Kei Hamade

Masaaki Tanimura

Yoichi Tobita

Takahiko Fukiage

Taku Hashimoto

Masaaki Nakatsuji

Daisuke Tagawa

Tsukasa Saika

Koshiro Tamaoki

Provided are: a capsule for non-ferrous metal collection that can collect a non-ferrous metal; and a method for collecting a non-ferrous metal using same. The capsule for non-ferrous metal collection comprises capsule contents and a covering section covering the capsule contents, and collects a non-ferrous metal within the capsule for non-ferrous metal collection by means of the capsule for non-ferrous metal collection being immersed in a solution containing a non-ferrous metal.

Capsule for non-ferrous metal collection and method for collecting non-ferrous metal

There are provided a control signal generation circuit receiving an external instruction input in synchronization with a clock signal to generate a control signal for defining a data output period in response to the external instruction, and an output buffer circuit receiving data read from a memory array for output to an output node for the data output period, and there is further provided an output control circuit for controlling turning first, second and third transistors on and off, the output control circuit in the data out period turning on and off one of the first and second transistors complementarily in response to the read data and also turning on the third transistor in response to the control signal.

Synchronous semiconductor memory device with NOEMI output buffer circuit

Common circuit includes inactivation/activation circuits. Exclusive circuits include inverters IV , IV , IV and IV at the input portions thereof. When an SDR-SDRM is to be produced, inactivation/activation circuit outputs an inactivation signal DASL fixed to a ground voltage to exclusive circuit, while inactivation/activation circuit outputs a signal /OE inverted from an output enable signal OE to exclusive circuit. Inverters IV and IV in exclusive circuit then output a signal based on the signal /OE. Further, an N-channel MOS transistor and a P-channel MOS transistor in exclusive circuit are completely turned off, so that no through current flows from a power-supply node to a ground terminal in exclusive circuit. As a result, generation of the through current is prevented in an inactivated circuit.

Semiconductor memory device enabling selective production of different semiconductor memory devices operating at different external power-supply voltages

Pulses are generated using an edge of a clock signal applied from a low speed tester as a trigger, and internal clock signals are generated utilizing the pulses. Internal circuitry is operated in synchronization with the internal clock signals. Thus a synchronous semiconductor device operating at high speed can be tested using a low speed tester.

Clock synchronous semiconductor memory device allowing testing by low speed tester

In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.

Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein

In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.

Semiconductor memory device

A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal. The latch circuit provides data at a first clock cycle of a clock signal when the command data has a first value and provides data at a second clock cycle of the clock signal, which is later than the first clock cycle, when the command data has a second value.

Synchronous semiconductor memory including register for storing data input and output mode information

A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.

Semiconductor memory device with an internal voltage generating circuit

A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.

Semiconductor device having test function

A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

Semiconductor memory device and data transfer circuit for transferring data between a DRAM and a SRAM

A read enable signal OEMF activated in response to an input command is applied to an N minus 2 clock shift circuit included in an output control circuit for implementation of ZCAS latency. An output signal of the N minus 2 clock shift circuit and an internal mask instructing signal activated in response to an external mask instructing signal are logically processed and applied to a one-clock shift circuit. According to an output signal OEMQM of one-clock shift circuit, a data output enable signal OEM controlling activation/inactivation of an output buffer circuit is activated/inactivated. Data output controlling portion occupying area of a synchronous dynamic random access memory is reduced and timings of activation/inactivation of data output by different commands are made the same.

Synchronous semiconductor memory having read data mask controlled output

In a synchronous dynamic random access memory (SDRAM), one bank A is divided into banks A0 and A1, and two sets of writing-related circuits are arranged corresponding to each memory cell array bank and are capable of performing writing operation substantially independently. The first and second bits of write data applied successively from the outside world are applied alternately to write registers. Since the I/O line pair is connected to the selected memory cells in respective memory cell array banks after incorporation of the second bit data to be written is completed, the potential levels of the corresponding I/O line pair always change to the corresponding potential levels from the initial state in writing the first and second bit data.

Synchronous semiconductor memory device capable of reducing delay time

Growing community of inventors

Hyogo, Japan

Yasuhiro Konishi