Sanyo Electric Co., Ltd.

Tottori Sanyo Electric Co., Ltd.

Yasuhiro Kobayashi

Sadao Yoshikawa

Yoh Takano

Noriaki Kojima

Masanori Kajitani

Keiichi Rembutsu

Satoru Hiraga

An active matrix type liquid crystal display device capable of reducing power consumption and eliminating switching loss so as not to cause surge when stepwise changing the gate pulse supplied to a gate line during selection. The device includes, as the selection voltage supply circuit (), a first power source (VGH) for supplying a predetermined selection voltage and a second power source (VANA) for supplying voltage lower than the selection voltage by a predetermined value, so that voltage from the second power source is always applied to an output point (VG) of the selection voltage supply circuit and voltage from the first power source is superimposed during a time shorter than the selection period from the beginning of the selection time, thereby applying stepwise gate pulses (GPn, GPn+1, GPn+2, . . . ) to the predetermined selected gate lines (Xn, Xn+1, Xn+2, . . . ).

Gate driver for an active matrix liquid crystal display device

A semiconductor memory device is described that has an improved read characteristics. The semiconductor memory device includes a plurality of memory cells, a reference cell, a comparator located between the memory cells and the reference cell, and a discriminator coupled to the comparator. The comparator compares the actual signal equivalent to a value of a current flowing in each of the memory cells and reference signals equivalent to a value of a current flowing in the reference cell with each other to output a comparison result signal in each of data reading operation modes. The discriminator discriminates a value of data stored in each of the memory cells based on the comparison result signal. The discriminator includes a circuit shared for discrimination of a data value in each of the data reading operation modes.

Semiconductor memory device with improved read characteristics for data

A semiconductor memory device includes a plurality of memory cells each having a control gate, a source, a drain and a floating gate. A write control unit controls voltages applied to the control gates, the sources and the drains to write data in each memory cell. A write-current determining circuit is connected to the write control unit, for determining a write current flowing in the floating gate of each memory cell and controlling the write control unit in accordance with a determination result, such that data is written in each memory cell with a predetermined write current.

Non-volatile semiconductor memory device

Disclosed is a semiconductor memory device. The memory device includes a plurality of memory cells, and a write control unit for controlling voltages applied to the memory cells to write data in the memory cells. The memory device further includes a current detector, connected to the write control unit. The current detector being implemented for detecting a cell current flowing in each of the memory cells and controlling the write control unit based on the detected cell current value. In this manner, writing to the memory cells is permitted until desired data is rewritten in each memory cell.

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Gifu, Japan

Yasuhiro Kobayashi