Denso Corporation

Yasuhiro Kitamura

Nozomu Akagi

Tetsuo Fujii

Kazushi Asami

Hiroki Nakamura

Makoto Asai

Masakiyo Sumitomo

Hiroshi Fujimoto

Hiroyuki Ban

Hiroshi Maeda

Shoji Mizuno

Hiroshi Imai

Mitsuhiro Saitou

Toshio Sakakibara

Shinji Yoshihara

Makio Iida

Junji Oohara

Yasutomi Asai

Yoshiaki Nakayama

Yuuki Inagaki

Atsushi Komura

Kenji Kohno

A semiconductor device has a semiconductor substrate where a plurality of elements or penetration electrodes are arranged and a trench is arranged to insulate and separate the plurality of elements or penetrating elements by surrounding the plurality of elements or penetration electrodes. The trench is arranged to penetrate both sides of the semiconductor substrate, and has an inner part where a space is arranged. Accordingly, it is possible to configure a semiconductor device having a structure to suppress insulation breakdown while simplifying a manufacturing process and improving yield of product manufacture.

Semiconductor device and manufacturing method for the same

A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.

Method for manufacturing semiconductor device having SOI substrate

In a manufacturing method for a semiconductor device having a coil layer part on a substrate, two support substrates each having a flat surface are prepared, and a component member is formed on the flat surface of each of the support substrates. The component member includes a wiring portion having a predetermined pattern and an insulation film surrounding the wiring portion. The wiring portion is provided with a connecting portion exposing from the insulation film. A coil layer part is formed by opposing and bonding the component members formed on the support substrates to each other while applying pressure in a condition where the flat surfaces of the support substrates are parallel to each other. A coil is formed in the coil layer part by connecting the wiring portions through the connecting portions.

Semiconductor device capable of restricting coil extension direction and manufacturing method thereof

A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.

Semiconductor device including double-sided multi-electrode chip embedded in multilayer wiring substrate

A semiconductor device includes a semiconductor substrate, a vertical transistor, a horizontal transistor, a lead, wire-bonding pads, and penetrating electrodes. The semiconductor substrate has first and second surfaces and includes a first surface portion adjacent to the first surface. The vertical transistor includes first and second electrodes on the first surface and a third electrode on the second surface. The horizontal transistor includes first, second, and third electrodes on the first surface. The vertical transistor and the horizontal transistor further include PN junction parts in the first surface portion. The lead is disposed to the first surface and is electrically coupled with the first electrode of the vertical transistor. The wire-bonding pads are disposed on the second surface. The second electrode of the vertical transistor and the first to third electrodes of the horizontal transistor are electrically coupled with the wire-boding pads through the penetrating electrodes.

Semiconductor device including vertical transistor and horizontal transistor

Semiconductor device having SOI substrate and method for manufacturing the same

In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple trenches are formed on the rear side of the substrate, so that each trench reaches the main side of the substrate. After that, an insulating material is deposited over an inner surface of each trench to form an insulating layer in the trench, so that the element formation regions are isolated. Thereby, generation of cracks and structural steps in the substrate and separation of element formation regions from the substrate can be suppressed.

Semiconductor device having multiple element formation regions and manufacturing method thereof

A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

Power MOS transistor for absorbing surge current

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Chiryu, Japan

Yasuhiro Kitamura