Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Yasuhiro Kita

Kohei Ishizuka

Narimichi Maeda

Yoshitaka Takasaki

Osamu Yumoto

Masahito Kobayashi

Yoshimune Hagiwara

Takashi Akazawa

Yuzo Kita

Masahiro Koya

Yoshinori Nagoya

Shizuo Sugiyama

Yoshiro Kokuryo

Kazuhiko Takaoka

Jun'ichi Nakagawa

Junichi Nakagawa

Takeo Kusama

Nobuo Tsukamoto

A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation. If the second pair is selected, the conversion of the fixed (floating) point data to floating (fixed) point data is effected by normalizing the third data with the value of the exponent part of the fourth data.

Arithmetic logic unit for floating point data and/or fixed point data

In an adder for floating point data, two floating point data are adjusted so that the exponent parts have the same value and the resulting adjusted mantissa parts are added. A first shift signal is generated on the basis of the result of the added mantissa parts and having a value necessary for normalization of the addition result, and a second shift signal is generated having a value equal to the difference between the adjusted exponent part of the floating point data and a minimum value predetermined for an exponent of any floating point data at which underflow occurs. The result of addition of the adjusted mantissa parts is shifted on the basis of said second shift signal or said first shift signal depending on whether or not an underflow occurs.

Adder for floating point data suitable for digital signal processing

In a gain control circuit, an electric power calculating circuit is connected to a variable gain amplifier and a gain setting circuit for generating a gain control signal applied to the variable gain amplifier to control the gain thereof.

Electric power detecting circuit and gain control circuit using the same

A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor is capable of executing data input/output operations with an external circuit in the data format of the fixed point representation and of performing internal operations in the floating point representation format. Further, conversion of an operational result from fixed point representation to floating point representation, and vice versa, can be performed internally in accordance with program instruction.

Digital processor with floating point multiplier and adder suitable for

An equalizer apparatus suitable for use in a MODEM for receiving a signal having passed through a number of carrier-band lines is disclosed in which the number of carrier-band lines is detected from a training signal, and electrical connection of a fixed equalizer to a variable equalizer is controlled on the basis of the number of carrier-band lines, in order to form a precise, simple automatic equalizer apparatus.

Automatic equalizer apparatus

A signal processing system detects the transmission characteristics of a channel thereby to compensate the output waveform of the channel into the most-optimum state. The impulse response of the channel is detected by transmitting a code having a keen autocorrelation from the transmission end and by determining the correlation between the received signal of the code transmitted and the same code of the aforementioned code at a reception end.

Signal processing system having impulse response detecting circuit

A circuit for varying the gain of an amplifier circuit linearly in decibel by the use of a digital code signal varying linearly, wherein a resistance network to be connected between an amplifier having a fixed gain and an input or output portion for the amplification is connected and the gain of the amplifier as well as the values of resistance elements constituting the resistance network is set so that the transfer function of the amplifier circuit may become: ##EQU1## .

Gain control circuit

A variable equalizer whose frequency characteristic varies in a range of 1-1/Y(f).sup.2 when the gain x of a variable amplifier varies from 0 (zero) to .infin. (infinity), and which reduces the number of shaping networks for the variable frequency characteristic. It is constructed of a forward pass circuit which consists of a variable amplifier and a frequency-dependent first circuit connected in the order mentioned between input and output terminals, a feedback pass circuit which is dependent upon the frequency and which feeds-back an output of the variable amplifier to an input thereof, and a feed forward pass circuit which is independent of the frequency and which feeds forward part of the input of the variable amplifier to an output of the first circuit.

Variable equalizer

A variable equalizer is provided which, using a single variable resistor, can make compensations in both the directions of the gain side, and the loss side and can set a reference gain as desired. An input signal to be equalized is received as an antiphase input signal of a differential amplifier, an output signal which has been equalized is fed back to the antiphase input signal, and a difference signal between an in-phase input signal and the antiphase input signal is delivered as an output. A resistor is connected between an input terminal and ground, first and second impedance circuits and a variable resistor are connected between an intermediate point of the first-mentioned resistor and ground in the order mentioned, and a voltage at the junction point between the first and second impedance circuits is used as the in-phase input signal.

To form a simple and economical variable equalizer, the equalizer is constructed of a differential amplifier having two input terminals to which an input signal to be equalized and an equalized output signal derived from the output terminal are applied, a first impedance circuit connected between the differential amplifier and the output terminal, and a series circuit having a second impedance circuit and a variable resistor connected in series between the output terminal and a ground terminal.

A variable equalizer wherein a series circuit which consists of a voltage source and an impedance circuit having an impedance Z.sub.x is connected in parallel with a circuit for changing an input voltage into a current, and an impedance circuit having an impedance Z.sub.y is also connected in parallel with this current source. The voltage value of the voltage source is made one which is obtained by multiplying the current by a value proportional to 1/Z.sub.y, and the impedance circuit having the impedance Z.sub.y is endowed with a frequency characteristic.

A variable equalizer adapted to be fabricated in an integrated circuit structure and having improved compensation characteristics comprises a parallel connection of two circuits, one including a series connection of a first impedance circuit (impedance: Zy) and an input A.C. signal source circuit having a voltage v.sub.i, the other comprising a series connection of a second impedance circuit (impedance: Z.sub.x) and an A.C. signal source circuit having a voltage amplitude v.sub.z which is equal to v.sub.i (K/Z.sub.y).sup.2, where K is a constant, and the second impedance circuit, consists of a variable resistor.

In order to realize a precision variable equalizer of little errors by a simple circuit arrangement, a plurality of variable transmission circuits having variable transfer coefficients are connected in series between input and output terminals, and feed-back and feed-forward are applied from input and output sides of the respective variable transmission circuits to input and output portions of the variable equalizer through transmission networks having specified transfer characteristics.

An inductorless variable equalizer comprises input and output terminals. A first transmission network is situated in the forward path between the input and output terminals and has a variable transfer coefficient; second and third transmission networks are situated in the feedback and feedforward paths, respectively, between the input and output terminals. Each of these networks has a fixed transfer coefficient and the transfer coefficients of the feedback and feedforward networks having polarities opposite each other.

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Hachioji, Japan

Yasuhiro Kita