Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Other

Renesas Technology Corp.

Renesas Electronics Corporation

Ajinomoto Co., Ltd.

Sumitomo Sitix Corporation

Kenrich Petrochemicals, Inc.

Mitsubishi Denki Kabushiki

Toshiba Memory Corporation

Yasuhiro Kimura

Yoichiro Mitani

Toshiaki Iwamatsu

Yasuo Yamaguchi

Akihito Ohno

Hidekazu Yamamoto

Hideki Naruoka

Takuma Mizobe

Yoshiko Yoshida

Masashi Sakai

Takahiro Yamamoto

Hajime Yamazaki

Yuuichi Hirano

Kenichi Hamano

Shigehisa Yamamoto

Yasukazu Mukogawa

Shoji Yoshida

Takashi Takeuchi

Norio Ishitsuka

Hajime Watanabe

Takanori Tanaka

Shuhei Nakata

Atsushi Maeda

Hiroshi Ishida

Nobuyuki Tomita

Tomonori Yamaoka

Tetsuya Uchida

Takashi Kanazawa

Koichiro Sagawa

Toshio Komemura

Kazuhito Matsukawa

Hirotoshi Ise

Toshihiko Noguchi

Yu Nakamura

Takashi Zama

Natsuo Yamaguchi

Naoki Chiba

Hiroshi Koya

Susumu Abe

Hiroshi Shinyashiki

Akihito Ono

Toshiki Oono

Masato Toyota

Morihiko Kume

Keiji Yamauchi

Norioki Uyehara

Masafumi Katsumata

Masanori Gohara

Tsuneaki Fujise

Minoru Abiko

Mikio Kurihara

Satoru Nishi

Masaya Yamaguchi

Takehiko Kijima

The object of the present invention is to enhance the device yield of SiC epitaxial wafers. The SiC epitaxial wafer includes a drift layer which is a SiC epitaxial layer. The drift layer has a film thickness of 18 &#x3bc;m or more and 350 &#x3bc;m or less and has arithmetic average roughness of 0.60 nm or more and 3.00 nm or less, and the impurity concentration thereof is 1&#xd7;10/cmor more and 5&#xd7;10/cmor less.

SiC epitaxial wafer and manufacturing method of the same

A SiC substrate () has an off angle &#x3b8;&#xb0;. A SiC epitaxial layer () having a film thickness of Tm &#x3bc;m is provided on the SiC substrate (). Triangular defects () are formed on a surface of the SiC epitaxial layer (). A density of triangular defects () having a length of Tm/Tan &#x3b8;&#xd7;0.9 or more in a substrate off direction is denoted by A. A density of triangular () defects having a length smaller than Tm/Tan &#x3b8;&#xd7;0.9 in the substrate off direction is denoted by B. B/A&#x2264;0.5 is satisfied.

SiC epitaxial wafer, method for manufacturing SiC epitaxial wafer, SiC device, and power conversion apparatus

An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.

Silicon carbide epitaxial substrate and silicon carbide semiconductor device

A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases. The carrier concentration of the carrier concentration transition layer has the concentration gradient that falls within a predetermined concentration range lying between a first concentration gradient condition and a second concentration gradient condition.

Semiconductor wafer, semiconductor device, and method for producing semiconductor device

A method for manufacturing an SiC substrate includes: performing a CMP treatment on an SiC substrate; after the CMP treatment, capturing an image of a surface of the SiC substrate to detect a scratch; determining the SiC substrate as a good article when a length L of the scratch having a contrast value equal to or larger than a threshold value is not more than &#x3c0;(D/2)/A&#xd7;F/100, wherein the scratch having the contrast value equal to or larger than the threshold value in the image serves as a starting point of an epitaxial defect, a diameter of the SiC substrate is represented by D, a length of a long side of a device chip to be formed on the SiC substrate is represented by A, and an allowable defective rate caused by scratches is represented by F.

Method for manufacturing SiC substrate

A manufacturing method for manufacturing a silicon carbide epitaxial wafer includes: introducing a cleaning gas into a growth furnace to remove dendrite-like polycrystal of silicon carbide attached to an inner wall of the growth furnace; after introducing the cleaning gas, bringing a silicon carbide substrate in the growth furnace; and growing a silicon carbide epitaxial layer on the silicon carbide substrate by introducing a processing gas into the growth furnace to manufacture a silicon carbide epitaxial wafer, wherein the cleaning gas having fluid energy of 1.6E-4 [J] or higher is introduced into the growth furnace.

Manufacturing method and apparatus for manufacturing silicon carbide epitaxial wafer

A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG.. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.

Semiconductor device with suppressed crystal defects in active areas

A semiconductor substrate that prevents formation of particles from an edge part of the substrate. The substrate contains an on-substrate oxide film and an SOI layer stacked on the oxide film. A molten layer is formed on the edge part of the on-substrate oxide film and the SOI layer by mixing the SOI layer and the on-substrate oxide film to cover the edge part. An epitaxial layer may also be formed on the edge part of the on-substrate oxide film and the SOI layer to cover the edge part.

Semiconductor substrate with stacked oxide and SOI layers with a molten or epitaxial layer formed on an edge of the stacked layers

A defect inspecting device for a wafer is built in a positioning device for positioning a wafer , as a substrate to be processed, in a semiconductor manufacturing process. Light is irradiated on the wafer held on a vacuum holding base while rotating the wafer at least one rotation from a position where the wafer is positioned and the scattered light is received. An operation unit and a control unit judge that if the intensity of the scattered light exceeds a predetermined threshold, a defect is detected on the wafer

Defect inspecting device for substrate to be processed and method of manufacturing semiconductor device

A dicing lines is placed to overlap a slip created in a wafer, so that the slip extends within the dicing line.

Semiconductor wafer with a dicing line overlapping a defect

An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate ( ) in the direction of radiuses of the SOI substrate ( ) to bring a buried oxide film ( ) in the edge part of the SOI substrate ( ) into a silicon-rich state. Thus an SOI substrate ( ) is provided, where the buried oxide film ( ) has substantially been eliminated in the edge part.

Semiconductor substrate processing method

A substrate having a surface on which silicon is epitaxially grown; wherein the substrate is cut from an oxygen induced stacking fault generation area of a single crystal silicon rod grown by the Czochralski method.

Substrate for epitaxial growth

An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (,) in the direction of radiuses of the SOI substrate (,) to bring a buried oxide film (,) in the edge part of the SOI substrate (,) into a silicon-rich state. Thus an SOI substrate (,) is provided, where the buried oxide film (,) has substantially been eliminated in the edge part.

An object is to obtain a semiconductor wafer evaluation method and a semiconductor device manufacturing method having a reduced turn-around time and requiring no process apparatus and no dielectric breakdown characteristic evaluation device in evaluation of the dielectric breakdown characteristic of the oxide film. A sample wafer (1) is etched by using an SC-1 solution bath (2) to change process defects caused in the fabrication process including mirror polishing into pits. The number of pits is detected with a dust particle inspection system, and the dielectric breakdown characteristic of the sample wafer 1 can be evaluated by using the number of detected pits and previously obtained relations between the number of pits and the dielectric breakdown characteristic.

Semiconductor wafer evaluating method and semiconductor device

A monocrystalline silicon wafer is improved so as not to cause enhanced oxidation at the time of forming a gate oxide film. The monocrystalline silicon wafer includes a monocrystalline silicon substrate. The monocrystalline silicon substrate has potassium concentration of at most 2.times.10.sup.11 atoms/cm.sup.2 at an outer surface thereof.

Monocrystalline silicon wafer and method of thermally oxidizing a

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Tokyo, Japan

Yasuhiro Kimura