Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hitachi Device Engineering Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Vsli Engineering Corp.

Yasuhiro Kasama

Kazuyoshi Oshima

Kazuhiko Kajigaya

Shinji Udo

Eiji Miyamoto

Takashi Yamazaki

Yasunori Yamaguchi

Masashi Horiguchi

Ryoichi Hori

Kazuyuki Miyazawa

Akira Endo

Jun Etoh

Yuji Sakai

Hiroshi Yoshioka

Tetsurou Matsumoto

Makoto Morino

Shinichi Ikenaga

Mitsuhiro Takano

Sinichi Miyatake

Manabu Tsunozaki

Jiro Sawada

Hirokazu Saito

Atsushi Kumata

Hiroaki Kotani

Tetsu Udagawa

Masamichi Ishihara

Toshiyuki Sakuta

Gen Murakami

Ichiro Anjoh

Hiroshi Satoh

Kazuya Ito

Satoshi Oguchi

Youichi Matsuno

Atsusi Nozoe

Hiroyuki Uchiyama

Yoshinobu Nakagome

Yasushi Takahashi

Toshio Sasaki

Shinichi Miyatake

Hisashi Nakamura

Hidetoshi Iwai

Yasushi Kawase

Hiromi Matsuura

Toshio Maeda

Osamu Sakai

Masanori Tazunoki

Yoichi Matsuno

Tathunori Mushya

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.

Semiconductor memory having redundancy circuit

Semiconductor memory device having zigzag bonding pad arrangement

A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Sealed stacked arrangement of semiconductor devices

Growing community of inventors

Tokyo, Japan

Yasuhiro Kasama